Simulation Results: otp_ctrl

 
08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.18 %
  • code
  • 85.49 %
  • assert
  • 95.47 %
  • func
  • 92.59 %
  • line
  • 90.21 %
  • branch
  • 86.80 %
  • cond
  • 94.08 %
  • toggle
  • 92.49 %
  • FSM
  • 63.89 %
Validation stages
V1
96.15%
V2
96.28%
V2S
95.91%
V3
26.73%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.730s 58.885us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 10.620s 8897.659us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.660s 264.390us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 2.170s 89.558us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 8.780s 2341.757us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.220s 1757.710us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.700s 399.550us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 2.170s 89.558us 5 5 100.00
otp_ctrl_csr_aliasing 5.220s 1757.710us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.720s 85.420us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.230s 83.510us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 18.100s 2810.174us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 9.090s 2974.474us 300 300 100.00
partition_check 37 60 61.67
otp_ctrl_background_chks 33.890s 12215.622us 10 10 100.00
otp_ctrl_check_fail 40.910s 4830.969us 27 50 54.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 10.490s 4720.469us 30 30 100.00
partition_lock 30 30 100.00
otp_ctrl_dai_lock 35.840s 15518.668us 30 30 100.00
interface_key_check 10 10 100.00
otp_ctrl_parallel_key_req 44.160s 23965.879us 10 10 100.00
lc_interactions 210 210 100.00
otp_ctrl_parallel_lc_req 27.270s 13997.688us 10 10 100.00
otp_ctrl_parallel_lc_esc 28.960s 12669.287us 200 200 100.00
otp_dai_errors 24 25 96.00
otp_ctrl_dai_errs 51.380s 24444.527us 24 25 96.00
otp_macro_errors 6 10 60.00
otp_ctrl_macro_errs 20.840s 17635.923us 6 10 60.00
test_access 10 10 100.00
otp_ctrl_test_access 30.640s 19141.843us 10 10 100.00
stress_all 10 10 100.00
otp_ctrl_stress_all 375.890s 60186.200us 10 10 100.00
intr_test 10 10 100.00
otp_ctrl_intr_test 1.950s 45.423us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 2.650s 137.507us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 6.630s 2731.308us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 6.630s 2731.308us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 1.660s 264.390us 1 1 100.00
otp_ctrl_csr_rw 2.170s 89.558us 5 5 100.00
otp_ctrl_csr_aliasing 5.220s 1757.710us 1 1 100.00
otp_ctrl_same_csr_outstanding 6.410s 2144.280us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 1.660s 264.390us 1 1 100.00
otp_ctrl_csr_rw 2.170s 89.558us 5 5 100.00
otp_ctrl_csr_aliasing 5.220s 1757.710us 1 1 100.00
otp_ctrl_same_csr_outstanding 6.410s 2144.280us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
tl_intg_err 30 30 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
otp_ctrl_tl_intg_err 28.620s 20174.820us 25 25 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
otp_ctrl_tl_intg_err 28.620s 20174.820us 25 25 100.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 10.620s 8897.659us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 10.620s 8897.659us 10 10 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_dai_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 28.960s 12669.287us 200 200 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_lci_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 28.960s 12669.287us 200 200 100.00
sec_cm_kdi_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 28.960s 12669.287us 200 200 100.00
sec_cm_part_fsm_local_esc 206 210 98.10
otp_ctrl_parallel_lc_esc 28.960s 12669.287us 200 200 100.00
otp_ctrl_macro_errs 20.840s 17635.923us 6 10 60.00
sec_cm_scrmbl_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 28.960s 12669.287us 200 200 100.00
sec_cm_timer_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 28.960s 12669.287us 200 200 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_dai_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 28.960s 12669.287us 200 200 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_lci_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 28.960s 12669.287us 200 200 100.00
sec_cm_kdi_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 28.960s 12669.287us 200 200 100.00
sec_cm_part_fsm_global_esc 206 210 98.10
otp_ctrl_parallel_lc_esc 28.960s 12669.287us 200 200 100.00
otp_ctrl_macro_errs 20.840s 17635.923us 6 10 60.00
sec_cm_scrmbl_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 28.960s 12669.287us 200 200 100.00
sec_cm_timer_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 28.960s 12669.287us 200 200 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 9.090s 2974.474us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 27 50 54.00
otp_ctrl_check_fail 40.910s 4830.969us 27 50 54.00
sec_cm_part_mem_regren 30 30 100.00
otp_ctrl_dai_lock 35.840s 15518.668us 30 30 100.00
sec_cm_part_mem_sw_unreadable 30 30 100.00
otp_ctrl_dai_lock 35.840s 15518.668us 30 30 100.00
sec_cm_part_mem_sw_unwritable 30 30 100.00
otp_ctrl_dai_lock 35.840s 15518.668us 30 30 100.00
sec_cm_lc_part_mem_sw_noaccess 30 30 100.00
otp_ctrl_dai_lock 35.840s 15518.668us 30 30 100.00
sec_cm_access_ctrl_mubi 30 30 100.00
otp_ctrl_dai_lock 35.840s 15518.668us 30 30 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 10.620s 8897.659us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 30 30 100.00
otp_ctrl_dai_lock 35.840s 15518.668us 30 30 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 10.620s 8897.659us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 176.360s 44008.967us 5 5 100.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 10.490s 4720.469us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 10.620s 8897.659us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 10.620s 8897.659us 10 10 100.00
sec_cm_macro_mem_integrity 6 10 60.00
otp_ctrl_macro_errs 20.840s 17635.923us 6 10 60.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 11.900s 3587.626us 1 1 100.00
stress_all_with_rand_reset 26 100 26.00
otp_ctrl_stress_all_with_rand_reset 136.220s 21226.624us 26 100 26.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 46 test runs
otp_ctrl_macro_errs 108119261415426805149518210248463943290569059334445405564745003428266750492946 9148
UVM_INFO @ 17635923129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 30321485271935327785089197650751998643850729293443555798515577824043453500476 615
UVM_INFO @ 77125993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 79631962361054688221378974584948753073467953429924807359815139858628911747938 12791
UVM_INFO @ 1217674482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 17616968568943251274630084761295375844505050015638638513823100338736612040378 193
UVM_INFO @ 196160125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 92910184866689861308626876615250046662331637871024832765835063986016294267149 4088
UVM_INFO @ 489612652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 27134961713447213379567273358267690136109517815815857610973676238796057467977 3993
UVM_INFO @ 690889040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 65485427580169177956964212044705218115026801759008153385292933970396728450496 3537
UVM_INFO @ 218431333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 31971391995453909793153416677181081258461583172868045594236942325364399087392 249
UVM_INFO @ 170266160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 93666269237846070341199311748888806987029788131974563653241161194993140490802 151
UVM_INFO @ 75961930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 113551519972893447054744949493858840696973170740098347620380898416412548939170 28477
UVM_INFO @ 1933947701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 95326032575993902691877233330284993005437058697028947233717946196492995686910 19144
UVM_INFO @ 5930094449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 40982824594693898913841168166749746827499367573446074311940410839339181323158 441
UVM_INFO @ 209869102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 26246047910415299336848229021160889692690299315384948637017136935077268043708 2591
UVM_INFO @ 266750782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 59565358800019542413478795644106330053543600537404696383405191659082728988371 5273
UVM_INFO @ 7577994898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91547212024433382844492486019319405178459053761069763555720886411716010620413 25270
UVM_INFO @ 875696952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 77284054570687466695607354416016055015136593439364503082499354759462190889409 5353
UVM_INFO @ 665269742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 16211918935646740407150841480392855808040435674819457852787887693102857417722 601
UVM_INFO @ 567320433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 41126337970247295278309346131046592547769999251742705422673259123540024943538 579
UVM_INFO @ 90969965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 112184939273829012230864047879328211871259845897507754593988318633016892066520 367
UVM_INFO @ 243542995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 6643198283316037919182479533991009441551745799492116042791235602354865958740 5480
UVM_INFO @ 270448538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 93957780541569737519254255894936769223774096150504357234990795421492968858234 6351
UVM_INFO @ 787627864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 48461866881813807128198207240125996658674091912339881889567241540350307993692 637
UVM_INFO @ 46358296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 78598975948133821784539541789431695889991166258372631764565485505363145216134 12049
UVM_INFO @ 3704197799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 108780830503943812439583297691414401454244416610749661262276441363983520298985 5441
UVM_INFO @ 847264615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 38046308610858163240528136136156882645472231960006044129721586475805014721952 4755
UVM_INFO @ 857530306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 78957067725552014854956005896535366680319400374446152000794214870401153178767 2649
UVM_INFO @ 652089996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 48173530396421382092275595705294724664773878765610860509526319407457042879612 10593
UVM_INFO @ 2457125233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 66630997697843150789899150551234980216170823702137367715063591423670314435744 638
UVM_INFO @ 603903487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 63125909855738388119606297368691919918550120644511291941102854965366930269143 547
UVM_INFO @ 247267048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 103049696138618719407498033806999802008675937094508761678048141141215529510620 273
UVM_INFO @ 617027267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1085720357862523946209683402177365834955641354663215622629236400267928861582 21979
UVM_INFO @ 6737403785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42974207855591825431938467791188166476717711603966127825099861286166799396335 743
UVM_INFO @ 385786529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 102850929773913430732327646115877696554698921064487440577342640332607497756023 6562
UVM_INFO @ 2236650015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 73706966149242034912889753798433245362931211259339085510687410842491159294855 3735
UVM_INFO @ 3426247754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 93094498824777678332125659013284676510155987391801092594874316785728486637882 3195
UVM_INFO @ 1579901289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 17325505943056329672760888388381391636249234844570629763619236730582579379817 2454
UVM_INFO @ 4063041595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 97329859185740234801610528734615326991479621523337542546462774906826329641069 5154
UVM_INFO @ 1413796668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29387612240780491678452237609945183248821323865759906964843714534676331853097 413
UVM_INFO @ 5347426868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25193895713838161012348400206051476192885657299114073511182910743221384492728 3370
UVM_INFO @ 2518502445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 32700792601951452353691055528021561959923622795665068940004800647611854816015 14383
UVM_INFO @ 2794141291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 9933918350660894551865662311462556986119091837568774431817967818382399170505 4564
UVM_INFO @ 7956968370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 93344606342455525840886009546906859351843994924689265659120862474639084936203 12484
UVM_INFO @ 10922215838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 46991026806707828921173981197658993148204517552757084167355976773558159152156 205
UVM_INFO @ 61393712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 24798727922199185656850413512691352987947499054726950138601464627271412331879 10880
UVM_INFO @ 6619320380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 58246600654328744795310511852817244258835289052163339558431533071138649931947 17498
UVM_INFO @ 8321192481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 70695897895547752925108171434071531299834533531093033855643620702657112307635 3947
UVM_INFO @ 17465020537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 22 test runs
otp_ctrl_stress_all_with_rand_reset 70851383380701588057846331664790059923537195569486384483931695874252830037696 1778
UVM_INFO @ 818931487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89683175681701454625013414863611817042290192728590051076676972666752835337158 25360
UVM_INFO @ 3415945970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 108814185877741922669424115205665600316773424127188214229198222665493064725729 5336
UVM_INFO @ 11747805935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 107760418795049271159689328354873766255654135736303711585259158638271346069684 7399
UVM_INFO @ 5200249689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 72229755291265281112622327702012436799313486536113748106698229813375735080107 4012
UVM_INFO @ 594879104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 97295013222547073982570065123628394054257656557134595677955723785275956021766 14977
UVM_INFO @ 48023413903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 16755056962957472454299405865641799975196770234180385767458669777080177667040 351
UVM_INFO @ 576977664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89728018599101056705387118491268722315040063309249834152176276541245035443449 3936
UVM_INFO @ 11752621689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 92951868010044287391295302285414204053415205532409818125495689014915414224939 12273
UVM_INFO @ 10449813803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84129049042979563731163724947257908371402172769061674143028148220120157538990 243
UVM_INFO @ 296650019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 60742139398481181604236058987464478958621142425735863511323143515736342368997 2523
UVM_INFO @ 409338843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 7829178657211536914957641884114972019101240471592650916722317261155514358978 10658
UVM_INFO @ 2406326879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104525685117038320461640681732380956967066393663430317557012823675748292606718 197
UVM_INFO @ 148285796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 92355527943951484214606841288275408505552232348687800915210756642087167302220 896
UVM_INFO @ 355011274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 74581000628155947586072311646400325368675679104362688776126097893089196244872 5027
UVM_INFO @ 3165807683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 24922524198784976227787641629903761050621287920789989748529259429599260534334 197
UVM_INFO @ 3865486488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50849345448027645416720751761533228761904808623389074274854676411944492770982 19155
UVM_INFO @ 2595328478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 58518639381974059498530466607676918339916018035124769654767777301456684400146 6341
UVM_INFO @ 18777709423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12573224537860296285856705120155659198823409196038553770871436395910683385353 16908
UVM_INFO @ 3717886376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38863693887070914976244386525830428678742103618949301623300912869004039992683 10410
UVM_INFO @ 7633425416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86043566925096942006271100592414412273977623763713906147919247968802552929941 435
UVM_INFO @ 1592400528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73392117134964177949709293227763323397188749517934632370329132792901578725240 15278
UVM_INFO @ 6572921712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1831) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 22 test runs
otp_ctrl_stress_all_with_rand_reset 56040241300326988815195058655699646615013869538283255038498963738782791272848 531
UVM_INFO @ 292945717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53126911009864372392881865253597412924136322571444158122794114109885163767079 92
UVM_INFO @ 107449905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 52753658454995665343346810724715451182586928793475401404475057566577517694148 92
UVM_INFO @ 429353984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 7073072973254964221012091236825322784021199427151992041705886047152591911444 93
UVM_INFO @ 57260877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 34757753433623092830759325915330573894419958213721763788629708405534211875072 46611
UVM_INFO @ 5590371327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 11373148493952269045442020860303425401601640685708155540357725774869497791100 13048
UVM_INFO @ 817595031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13223613714818366930463240896794744237501524842707867000862954681627610227876 18139
UVM_INFO @ 10831556846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 21841327741802165788750841905422116372661011733058809854599943831443006651699 476
UVM_INFO @ 79973745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5091741774481581226902561626680354350976624095148131491140457293942676181623 4104
UVM_INFO @ 24750864211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23011546547362913385732343240511307850577798014168595473046974408755987142278 4005
UVM_INFO @ 2158115878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 78180336280895580327419923486966076539461280315662211133174850697249633122623 92
UVM_INFO @ 47356055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43388260180124592212546870207315936564245617134119841155904986157270427327398 93
UVM_INFO @ 53638222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 109887533993300520836688326697782140821584002165994379146395871594026384555854 150
UVM_INFO @ 114545119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63360774457893487864695783935766676922426025536604209970699692903264102545385 46905
UVM_INFO @ 10857979218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53089261768461382662479129228074819318108310242756902384901907844290214517775 92
UVM_INFO @ 30111608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 14969560626754500930175997967852735752571606235197416033751238870646695429611 92
UVM_INFO @ 425386527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45635605112048126713236243987336990971968838402525495700455301818217951002966 2654
UVM_INFO @ 2187311992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 47086412252543961529279577196883230912139484203989163465692151131436788149705 18832
UVM_INFO @ 12953529897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29712243142204933974691261407109784527430189896632517602789029863819417361539 33874
UVM_INFO @ 2527545230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25963591931031111651022283282627191613417169147787122792147063931183512210616 92
UVM_INFO @ 43356804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 67404028520050823613709228208179890313438021685425739422670453499491666938902 5361
UVM_INFO @ 484086208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86706217152330893939611268209675251653529026972149709098957364718878721638312 27215
UVM_INFO @ 1399025607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:672) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 9 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 64212697490632219182770924998359642937180375631185447559573591560151090376292 92
UVM_INFO @ 430607233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 94684245922905833573797595591360351178748216289486529011061237155100993849147 11144
UVM_INFO @ 1038534486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 102587109872717638187024791074588791307517945231053753005812682356989832405659 92
UVM_INFO @ 116493272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 19483800017865786311343757408693914654849934631393470125344447111358372049410 92
UVM_INFO @ 51554349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81877151827035774844251085464084500773826867882568398402518696054754693064283 8230
UVM_INFO @ 1727343009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 16166437471165850051418311761641367907730677964203529493456446301473045889553 12760
UVM_INFO @ 9295147772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86916636464365720206991372248042128221725080878435607217847669406602413243621 10036
UVM_INFO @ 12863290922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45390240461220173211171940212151741575156018365356385249622492306356987746284 92
UVM_INFO @ 30040158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89323473133673037581435893682618206619286289894491097514146602035290000219939 1126
UVM_INFO @ 517051278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' 1 test run
otp_ctrl_stress_all_with_rand_reset 51983837098386830008326611813290902745097313256100744207573247857439183042854 12025
UVM_ERROR @ 2418474057 ps: (otp_ctrl_if.sv:299) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 2418474057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 29396099168226057007776411877513241453958157017610665057092401809012526023234 12636
UVM_INFO @ 9140188001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:283) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) 1 test run
otp_ctrl_stress_all_with_rand_reset 100310177391227687352495780609507642807520226455868371127111928479865372051278 1586
UVM_INFO @ 242606180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otp_ctrl_stress_all_with_rand_reset 75111490252551545556208837800259516258652924388740758785651247712914552288299 12571
UVM_INFO @ 18809150719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---