Simulation Results: pwrmgr

 
08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.50 %
  • code
  • 97.54 %
  • assert
  • 98.96 %
  • func
  • 99.01 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.61 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
94.89%
V2S
100.00%
V3
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 0.900s 24.893us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.770s 54.546us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 0.760s 23.450us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.450s 220.387us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.290s 51.676us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.150s 58.075us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 0.760s 23.450us 5 5 100.00
pwrmgr_csr_aliasing 1.290s 51.676us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 1.180s 138.323us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 1.180s 138.323us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 0.940s 212.611us 10 10 100.00
pwrmgr_lowpower_invalid 0.870s 58.577us 10 10 100.00
reset 16 20 80.00
pwrmgr_reset 2.530s 1000.000us 9 10 90.00
pwrmgr_reset_invalid 0.950s 102.029us 7 10 70.00
main_power_glitch_reset 9 10 90.00
pwrmgr_reset 2.530s 1000.000us 9 10 90.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.520s 286.783us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.170s 235.402us 10 10 100.00
disable_rom_integrity_check 10 10 100.00
pwrmgr_disable_rom_integrity_check 1.100s 174.167us 10 10 100.00
stress_all 7 10 70.00
pwrmgr_stress_all 28.860s 10246.806us 7 10 70.00
intr_test 10 10 100.00
pwrmgr_intr_test 0.810s 41.108us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwrmgr_tl_errors 2.290s 721.679us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwrmgr_tl_errors 2.290s 721.679us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 0.770s 54.546us 1 1 100.00
pwrmgr_csr_rw 0.760s 23.450us 5 5 100.00
pwrmgr_csr_aliasing 1.290s 51.676us 1 1 100.00
pwrmgr_same_csr_outstanding 0.980s 79.235us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 0.770s 54.546us 1 1 100.00
pwrmgr_csr_rw 0.760s 23.450us 5 5 100.00
pwrmgr_csr_aliasing 1.290s 51.676us 1 1 100.00
pwrmgr_same_csr_outstanding 0.980s 79.235us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
pwrmgr_tl_intg_err 1.540s 243.724us 25 25 100.00
pwrmgr_sec_cm 1.510s 611.454us 5 5 100.00
prim_count_check 5 5 100.00
pwrmgr_sec_cm 1.510s 611.454us 5 5 100.00
prim_fsm_check 5 5 100.00
pwrmgr_sec_cm 1.510s 611.454us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
pwrmgr_tl_intg_err 1.540s 243.724us 25 25 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.110s 884.919us 10 10 100.00
sec_cm_rom_ctrl_intersig_mubi 20 20 100.00
pwrmgr_wakeup_reset 1.520s 286.783us 10 10 100.00
pwrmgr_repeat_wakeup_reset 2.150s 833.213us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.100s 51.645us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 0.850s 29.294us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 5 5 100.00
pwrmgr_sec_cm 1.510s 611.454us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
pwrmgr_sec_cm 1.510s 611.454us 5 5 100.00
sec_cm_fsm_terminal 5 5 100.00
pwrmgr_sec_cm 1.510s 611.454us 5 5 100.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 0.760s 31.202us 10 10 100.00
sec_cm_main_pd_rst_local_esc 10 10 100.00
pwrmgr_glitch 0.820s 48.101us 10 10 100.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.230s 257.679us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.760s 23.450us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.760s 23.450us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 5 10 50.00
pwrmgr_escalation_timeout 0.970s 371.004us 5 10 50.00
stress_all_with_rand_reset 10 10 100.00
pwrmgr_stress_all_with_rand_reset 11.360s 28695.606us 10 10 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 4 test runs
pwrmgr_escalation_timeout 12784188448903566191565850720789374531441685246807641284611188406051953707995 79
UVM_ERROR @ 371003650 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 371003650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 81145619260610234041281300942108720123867574857508778530827820122369104986563 79
UVM_ERROR @ 103121091 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 103121091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 493914679509786442879363639474915096431208860293996108981201418152937695751 79
UVM_ERROR @ 188872973 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 188872973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 76940118388354551863678870181918239229353068998496551572722404717389866997812 79
UVM_ERROR @ 371166052 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 371166052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 3 test runs
pwrmgr_stress_all 97810057872622876385895127959727708620529388586634718295973922955471644240529 165
UVM_INFO @ 10202404448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 2806137512834889961028247114767508632311779685047327981611382592287554146178 198
UVM_INFO @ 10246806076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 16758014163752915988264821340126228834391249763883457041587912447616572285684 114
UVM_INFO @ 10044847653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 83123626320116946913553610176251109085184939386860148135948906019006632920423 152
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitRomCheck 1 test run
pwrmgr_reset_invalid 86879212099369036143633447867969359615627737300663214626269515280041998993593 117
UVM_INFO @ 94965939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pwr_rst_o.rst_lc_req == *'b11)' 1 test run
pwrmgr_escalation_timeout 96216014546419388509733230581587039727617718756899807215146990043732949600029 76
UVM_ERROR @ 96984225 ps: (pwrmgr.sv:178) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
UVM_INFO @ 96984225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitLcInit 1 test run
pwrmgr_reset_invalid 111623786731963586266610376099279142813287502269823172747208102325596991913473 143
UVM_INFO @ 83969112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitOtpInit 1 test run
pwrmgr_reset_invalid 15463741485514928877540352815480585343931867588074957274287847240544390334756 203
UVM_INFO @ 70200519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---