Simulation Results: rom_ctrl/64kb

 
08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.53 %
  • code
  • 92.64 %
  • assert
  • 97.68 %
  • func
  • 99.28 %
  • line
  • 98.66 %
  • branch
  • 99.27 %
  • cond
  • 96.58 %
  • toggle
  • 95.34 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
97.18%
V2S
66.10%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 8.910s 398.747us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.440s 87.989us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 5.230s 52.019us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.690s 117.022us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.890s 53.527us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.990s 64.725us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 5.230s 52.019us 5 5 100.00
rom_ctrl_csr_aliasing 3.890s 53.527us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.640s 178.840us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.780s 55.645us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 8.130s 342.269us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 39.280s 1436.198us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 16.030s 939.700us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 5.490s 57.868us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 12.350s 1086.374us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 12.350s 1086.374us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 8.440s 87.989us 1 1 100.00
rom_ctrl_csr_rw 5.230s 52.019us 5 5 100.00
rom_ctrl_csr_aliasing 3.890s 53.527us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.300s 58.029us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 8.440s 87.989us 1 1 100.00
rom_ctrl_csr_rw 5.230s 52.019us 5 5 100.00
rom_ctrl_csr_aliasing 3.890s 53.527us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.300s 58.029us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.159s 0.000us 0 20 0.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.560s 4143.425us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 593.450s 533.270us 5 5 100.00
rom_ctrl_tl_intg_err 137.540s 736.765us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 593.450s 533.270us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 593.450s 533.270us 5 5 100.00
sec_cm_checker_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.159s 0.000us 0 20 0.00
sec_cm_checker_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.159s 0.000us 0 20 0.00
sec_cm_checker_fsm_local_esc 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.159s 0.000us 0 20 0.00
sec_cm_compare_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.159s 0.000us 0 20 0.00
sec_cm_compare_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.159s 0.000us 0 20 0.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 593.450s 533.270us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 593.450s 533.270us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 8.910s 398.747us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 8.910s 398.747us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 8.910s 398.747us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 137.540s 736.765us 25 25 100.00
sec_cm_bus_local_esc 2 22 9.09
rom_ctrl_corrupt_sig_fatal_chk 3600.159s 0.000us 0 20 0.00
rom_ctrl_kmac_err_chk 16.030s 939.700us 2 2 100.00
sec_cm_mux_mubi 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.159s 0.000us 0 20 0.00
sec_cm_mux_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.159s 0.000us 0 20 0.00
sec_cm_ctrl_redun 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.159s 0.000us 0 20 0.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.560s 4143.425us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 593.450s 533.270us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 286.520s 6158.685us 20 20 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 8 test runs
rom_ctrl_corrupt_sig_fatal_chk 47715037969746098668589090598392311835057709283494410225401708881653598989640 None
rom_ctrl_corrupt_sig_fatal_chk 57586405796293800665466096543332557709457858485904768624630035132040726841057 None
rom_ctrl_corrupt_sig_fatal_chk 30566104245583986847434968735322495049702377161983129689542580806724300491713 None
rom_ctrl_corrupt_sig_fatal_chk 105153145708408748138308468873865580671415660331631125125401346119672077351892 None
rom_ctrl_corrupt_sig_fatal_chk 62078281005523585119620246059196170663451254130849031143442018073780911614299 None
rom_ctrl_corrupt_sig_fatal_chk 28141921784019579840378704757722566148811619499969582682870110359880628326024 None
rom_ctrl_corrupt_sig_fatal_chk 101250690868880673812418109184602812815084558301678059655301819039285903207531 None
rom_ctrl_corrupt_sig_fatal_chk 17065848902589520372747896808219356640309001668495451459956948960174551824998 None
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] Expected alert (fatal) did not fire in * cycles. 4 test runs
rom_ctrl_corrupt_sig_fatal_chk 47878853895451504851902559016725924267046336283780865955781623709187427750481 78
UVM_INFO @ 69234275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 42644678121076928895823902612190838619061127361658981088738527085105601793099 78
UVM_INFO @ 53908772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 86633705386428259385090636411484363010993237986922627134069913903601754841616 87
UVM_INFO @ 120362878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 114327654149905862385605934611372988983041063200390003816642707549633880250495 80
UVM_INFO @ 1424519156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:295) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.compare_vif.is_waiting()) 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 76302811720029228527666299289633465871967768822325889174808341291214249314719 78
UVM_INFO @ 1983560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 12326963535079528817010836782495917134201686164459677355393783755622322580972 78
UVM_INFO @ 1654554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 90203126752704308251537632073372308412777694366578051609040016049218169665608 78
UVM_INFO @ 6297361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 25453174916319221195356052976346794533263816960292948404679366479604178306272 79
UVM_INFO @ 35466164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 44466323596229173204685055549838790422933537491104469086386170537386493203226 79
UVM_INFO @ 342268828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:148) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 8843120679160937403878226423464752742081522136525425522605403198740169796470 80
UVM_INFO @ 189405577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 34534617094637591216330588880321697504240844531492676179404632030902835704981 83
UVM_INFO @ 9237958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:278) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.fsm_vif.get_fsm_state() == rom_ctrl_pkg::ReadingLow) 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 45524439597746859163151762922071842152974159066745252860163389641720087402203 86
UVM_INFO @ 35196050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 20740117336850096316103611362260414536259026804235384206589640773953752694503 84
UVM_INFO @ 86955573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:303) scoreboard [wrong_pwrmgr_good] rom_ctrl is reporting good=* (MuBi4True) to the pwrmgr, but we expected * (MuBi4False). 1 test run
rom_ctrl_corrupt_sig_fatal_chk 83902526758000381130510569167693542784885552129026305643899197019103211900298 80
UVM_INFO @ 50099351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---