| V1 |
|
100.00% |
| V2 |
|
88.19% |
| V2S |
|
100.00% |
| V3 |
|
47.50% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 2.540s | 2362.429us | 20 | 20 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.770s | 13.462us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rv_timer_csr_rw | 0.850s | 19.402us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 2.320s | 560.649us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 1.210s | 126.761us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.110s | 98.690us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rv_timer_csr_rw | 0.850s | 19.402us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.210s | 126.761us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 5 | 20 | 25.00 | |||
| rv_timer_random_reset | 6.960s | 1679.336us | 5 | 20 | 25.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 3.080s | 2030.514us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 348.810s | 906088.403us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 348.810s | 906088.403us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 8.930s | 4966.787us | 20 | 20 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rv_timer_alert_test | 0.820s | 12.603us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| rv_timer_intr_test | 0.890s | 214.186us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 3.180s | 175.608us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 3.180s | 175.608us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.770s | 13.462us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.850s | 19.402us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.210s | 126.761us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.940s | 21.117us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.770s | 13.462us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.850s | 19.402us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 1.210s | 126.761us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 0.940s | 21.117us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rv_timer_sec_cm | 1.180s | 833.207us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.730s | 243.876us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rv_timer_tl_intg_err | 1.730s | 243.876us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 2 | 10 | 20.00 | |||
| rv_timer_min | 5.610s | 1753.870us | 2 | 10 | 20.00 | |
| max_value | 2 | 10 | 20.00 | |||
| rv_timer_max | 1.470s | 42.022us | 2 | 10 | 20.00 | |
| stress_all_with_rand_reset | 15 | 20 | 75.00 | |||
| rv_timer_stress_all_with_rand_reset | 39.190s | 4295.088us | 15 | 20 | 75.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | 23 test runs | |||
| rv_timer_min | 52515039843798333098161716207270412437918212978289491214178087246071468265210 | 78 |
UVM_INFO @ 777411859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 20641882908332146988078151910358559383449076014628558232428607637947759166569 | 75 |
UVM_INFO @ 75913934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 44546864568213735267483540548014799089279595255564452242791693001038581325082 | 76 |
UVM_INFO @ 1762185747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 85087490901288999899572897298527525108815212413493880077630170911058882559309 | 76 |
UVM_INFO @ 482576306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 60457201268584603005700270621438409848272347105200334306750285831680972546289 | 75 |
UVM_INFO @ 1753869841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 88052475608825073180268873131900110045424359382345130209530761084365799743899 | 75 |
UVM_INFO @ 512361097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 100777791687813835119325329775702842262397698485798530536763503296094004361508 | 77 |
UVM_INFO @ 686888760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 111111157842590337817631266399094885972071267934519855496089959132119030943860 | 75 |
UVM_INFO @ 1649205478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 86462408656988090165673163322770743716875846808604933599400368621888075341133 | 75 |
UVM_INFO @ 70049202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 69032458014395729210767082197685590789080050494414964991844223574344808178894 | 75 |
UVM_INFO @ 229827515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 35849480772834657391736328232287012039929484138463708549893494209618871543903 | 77 |
UVM_INFO @ 241796295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 12836946628830244407316244085574010806486597861976591813260407756750016169732 | 76 |
UVM_INFO @ 277997354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 105937677293035820901218840254105769773475941502094814143079388243336500451332 | 78 |
UVM_INFO @ 67241663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 75542692895099036978110254988465377225462987874118798127350832830097314106108 | 76 |
UVM_INFO @ 619115571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 78795272097509969856993350321493800527589724515844363659498596339245751085531 | 76 |
UVM_INFO @ 73519524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 12227711786125241497645220273768007706668237092684165834678509537379890417287 | 75 |
UVM_INFO @ 341470716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 26195100046404421631273781659595107838827606592945259507454328049825112393432 | 75 |
UVM_INFO @ 1679336290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 26501030192835110758445583441174102142305635308615176841731265690742220071061 | 76 |
UVM_INFO @ 644222577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 112159644890092333895484293832261455016857038065876039969913245706800255709883 | 75 |
UVM_INFO @ 63419072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 112522229753066577314993028994611294455008323911157844918988460962305826419687 | 75 |
UVM_INFO @ 1807157262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 90558852686086175743144264943511995062880594182695616644471345103202649481446 | 75 |
UVM_INFO @ 131762134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 52528002240877571590446957554251627536734373213437746401779055508342466543529 | 75 |
UVM_INFO @ 519511574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 50023612186988692846205047936599069439301597501113182497055660522617148925676 | 76 |
UVM_INFO @ 753093057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 8 test runs | |||
| rv_timer_max | 88674322016078133826446479713878307883846158652880337740142565166487943851567 | 75 |
UVM_INFO @ 88048820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 57909507253301460422692996664457801804398045928877378813634179347108584387867 | 75 |
UVM_INFO @ 45174884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 17759464005138440844625449866190913101010173569362590249988521978609944524557 | 75 |
UVM_INFO @ 164281432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 33344612225691132699095425750496978729866512988588153598442728600101976530392 | 77 |
UVM_INFO @ 188415025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 114235908037646503336285428192367246647004250565241351033519027075343997119864 | 75 |
UVM_INFO @ 46748330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 43541640077142239612000107441809310101048345705517903298368240093748585761457 | 75 |
UVM_INFO @ 42022430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 106562808394759510624701787470641927667014899733372878334041090093237074890586 | 75 |
UVM_INFO @ 262656176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 14763323395631839998273250638807718964388408878006964657449444115176916694288 | 75 |
UVM_INFO @ 350706466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) | 4 test runs | |||
| rv_timer_stress_all_with_rand_reset | 15201403525010793784502712272658823974185588374418840978913309567287002347124 | 121 |
UVM_INFO @ 842184010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 6249441849413719975268990308882693704755559809890695611986998365023638016857 | 316 |
UVM_INFO @ 4604974058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 95808255303003870544276037277597807500286197589263991016636657180328901815295 | 129 |
UVM_INFO @ 751059467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 62370722786169744380050020879574720964944092947039197063304956765867170822900 | 376 |
UVM_INFO @ 29729888555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 1 test run | |||
| rv_timer_stress_all_with_rand_reset | 10989566461359956801366940645113822680939333248830901432464430062241031791692 | 107 |
UVM_INFO @ 444740589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|