Simulation Results: spi_host

 
08/08/2026 02:25:00 DVSim: v1.49.0 sha: d313c71 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.95 %
  • code
  • 91.30 %
  • assert
  • 96.79 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.35%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 51.000s 1817.209us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 134.043us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 48.032us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 4.000s 49.574us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 4.000s 32.325us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 50.566us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 48.032us 5 5 100.00
spi_host_csr_aliasing 4.000s 32.325us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 32.864us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 72.772us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 19.766us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 11.000s 1033.426us 10 10 100.00
spi_host_error_cmd 2.000s 85.075us 10 10 100.00
spi_host_event 113.000s 14644.832us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 4.000s 214.844us 10 10 100.00
speed 10 10 100.00
spi_host_speed 4.000s 214.844us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 4.000s 214.844us 10 10 100.00
upper_range_clkdiv 4 5 80.00
spi_host_upper_range_clkdiv 387.000s 200000.000us 4 5 80.00
sw_reset 10 10 100.00
spi_host_sw_reset 81.000s 3586.951us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 193.032us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 4.000s 214.844us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 4.000s 214.844us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 51.000s 1817.209us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 51.000s 1817.209us 10 10 100.00
stress_all 8 10 80.00
spi_host_stress_all 1841.000s 1000000.000us 8 10 80.00
spien 10 10 100.00
spi_host_spien 107.000s 8431.203us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 102.000s 12345.852us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 4.000s 662.015us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 11.000s 1033.426us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 3.000s 32.769us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 1.000s 60.149us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 3.000s 49.815us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 3.000s 49.815us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 134.043us 1 1 100.00
spi_host_csr_rw 2.000s 48.032us 5 5 100.00
spi_host_csr_aliasing 4.000s 32.325us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 93.020us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 134.043us 1 1 100.00
spi_host_csr_rw 2.000s 48.032us 5 5 100.00
spi_host_csr_aliasing 4.000s 32.325us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 93.020us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 301.708us 25 25 100.00
spi_host_sec_cm 2.000s 77.995us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 301.708us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 3 test runs
spi_host_upper_range_clkdiv 7501548771733354747252418657755634940581726295008660677567629969232192671028 136
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_stress_all 61968478939152300797904519112119997067909181959423457097752925807209616986438 153
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_stress_all 22148066929439076043976589451272040805576085921960972152595926703318931740079 230
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---