| V1 |
|
97.30% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 46.636us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 65.335us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 13.673us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 3.000s | 863.700us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 2.000s | 23.376us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 4 | 5 | 80.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 3.000s | 40.218us | 4 | 5 | 80.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 13.673us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 23.376us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 10.000s | 382.172us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 7.000s | 743.352us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 14.000s | 501.489us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 209.000s | 3962.064us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 11.000s | 4008.411us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 22.000s | 2560.222us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 7.000s | 3098.516us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 16.000s | 1203.422us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 3.000s | 51.828us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 336.000s | 295469.718us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 2.000s | 59.857us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 2.000s | 316.398us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 2.000s | 74.347us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 20.000s | 3967.089us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 2.000s | 140.749us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 44.000s | 3363.961us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 2.000s | 13.847us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 5.000s | 127.246us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 5.000s | 127.246us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 65.335us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 13.673us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 23.376us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 19.249us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 65.335us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 13.673us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 23.376us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 19.249us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 4.000s | 554.105us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 319.084us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 4.000s | 4379.703us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 319.084us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 4.000s | 4379.703us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 20.000s | 3967.089us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 20.000s | 3967.089us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 13.673us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 16.000s | 1203.422us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 16.000s | 1203.422us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 16.000s | 1203.422us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 7.000s | 3098.516us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_mubi_enc_err | 2.000s | 134.579us | 8 | 8 | 100.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 4.000s | 554.105us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 8 | 8 | 100.00 | |||
| sram_ctrl_readback_err | 2.000s | 122.134us | 8 | 8 | 100.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 46.636us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 46.636us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 16.000s | 1203.422us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 319.084us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 7.000s | 3098.516us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 319.084us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 319.084us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 46.636us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 319.084us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 49.000s | 1395.327us | 8 | 8 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) | 1 test run | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 48149384684119374352961120740798995135896714991648485952737895237452723484210 | 98 |
UVM_INFO @ 40218496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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