Simulation Results: adc_ctrl

 
15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.55 %
  • code
  • 98.54 %
  • assert
  • 96.76 %
  • func
  • 19.34 %
  • line
  • 99.05 %
  • branch
  • 98.51 %
  • cond
  • 95.12 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
adc_ctrl_smoke 15.780s 5742.050us 10 10 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.300s 565.503us 1 1 100.00
csr_rw 5 5 100.00
adc_ctrl_csr_rw 2.420s 556.079us 5 5 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 12.250s 52946.618us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.300s 887.083us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 2.120s 527.905us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
adc_ctrl_csr_rw 2.420s 556.079us 5 5 100.00
adc_ctrl_csr_aliasing 2.300s 887.083us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 10 10 100.00
adc_ctrl_filters_polled 140.010s 52046.770us 10 10 100.00
filters_polled_fixed 10 10 100.00
adc_ctrl_filters_polled_fixed 94.810s 54019.806us 10 10 100.00
filters_interrupt 10 10 100.00
adc_ctrl_filters_interrupt 105.320s 55069.251us 10 10 100.00
filters_interrupt_fixed 10 10 100.00
adc_ctrl_filters_interrupt_fixed 102.470s 53046.137us 10 10 100.00
filters_wakeup 10 10 100.00
adc_ctrl_filters_wakeup 150.480s 72955.509us 10 10 100.00
filters_wakeup_fixed 10 10 100.00
adc_ctrl_filters_wakeup_fixed 182.870s 74860.888us 10 10 100.00
filters_both 10 10 100.00
adc_ctrl_filters_both 66.500s 36871.908us 10 10 100.00
clock_gating 10 10 100.00
adc_ctrl_clock_gating 124.950s 65827.463us 10 10 100.00
poweron_counter 10 10 100.00
adc_ctrl_poweron_counter 13.300s 4883.444us 10 10 100.00
lowpower_counter 10 10 100.00
adc_ctrl_lowpower_counter 78.330s 38890.358us 10 10 100.00
fsm_reset 10 10 100.00
adc_ctrl_fsm_reset 195.190s 89366.863us 10 10 100.00
stress_all 10 10 100.00
adc_ctrl_stress_all 171.250s 109541.224us 10 10 100.00
alert_test 10 10 100.00
adc_ctrl_alert_test 2.090s 465.646us 10 10 100.00
intr_test 10 10 100.00
adc_ctrl_intr_test 1.300s 295.265us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
adc_ctrl_tl_errors 3.980s 538.871us 25 25 100.00
tl_d_illegal_access 25 25 100.00
adc_ctrl_tl_errors 3.980s 538.871us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
adc_ctrl_csr_hw_reset 2.300s 565.503us 1 1 100.00
adc_ctrl_csr_rw 2.420s 556.079us 5 5 100.00
adc_ctrl_csr_aliasing 2.300s 887.083us 1 1 100.00
adc_ctrl_same_csr_outstanding 18.460s 4372.820us 5 5 100.00
tl_d_partial_access 12 12 100.00
adc_ctrl_csr_hw_reset 2.300s 565.503us 1 1 100.00
adc_ctrl_csr_rw 2.420s 556.079us 5 5 100.00
adc_ctrl_csr_aliasing 2.300s 887.083us 1 1 100.00
adc_ctrl_same_csr_outstanding 18.460s 4372.820us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
adc_ctrl_sec_cm 16.060s 7991.998us 5 5 100.00
adc_ctrl_tl_intg_err 26.620s 8503.236us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
adc_ctrl_tl_intg_err 26.620s 8503.236us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
adc_ctrl_stress_all_with_rand_reset 22.980s 26562.869us 10 10 100.00