| V1 |
|
100.00% |
| V2 |
|
89.35% |
| V2S |
|
98.05% |
| V3 |
|
20.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 84.920s | 3119.691us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 5.730s | 60.127us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 7.060s | 266.513us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 477.120s | 111070.280us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 155.900s | 2230.068us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 12.310s | 763.350us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 7.060s | 266.513us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 155.900s | 2230.068us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 291.170s | 29058.293us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 78.210s | 1416.402us | 50 | 50 | 100.00 | |
| entropy | 24 | 25 | 96.00 | |||
| alert_handler_entropy | 3433.520s | 609284.239us | 24 | 25 | 96.00 | |
| sig_int_fail | 49 | 50 | 98.00 | |||
| alert_handler_sig_int_fail | 82.930s | 5659.283us | 49 | 50 | 98.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 84.920s | 3119.691us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 82.280s | 5528.862us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 77.260s | 1397.196us | 50 | 50 | 100.00 | |
| ping_timeout | 21 | 50 | 42.00 | |||
| alert_handler_ping_timeout | 615.150s | 27009.681us | 21 | 50 | 42.00 | |
| lpg | 97 | 100 | 97.00 | |||
| alert_handler_lpg | 3467.440s | 549761.953us | 48 | 50 | 96.00 | |
| alert_handler_lpg_stub_clk | 3161.760s | 279799.921us | 49 | 50 | 98.00 | |
| stress_all | 50 | 50 | 100.00 | |||
| alert_handler_stress_all | 4216.740s | 83755.324us | 50 | 50 | 100.00 | |
| alert_handler_entropy_stress_test | 0 | 20 | 0.00 | |||
| alert_handler_entropy_stress | 32.560s | 715.734us | 0 | 20 | 0.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 5.610s | 249.998us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.410s | 13.461us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 33.730s | 1182.953us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 33.730s | 1182.953us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 5.730s | 60.127us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 7.060s | 266.513us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 155.900s | 2230.068us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 58.430s | 704.093us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 5.730s | 60.127us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 7.060s | 266.513us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 155.900s | 2230.068us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 58.430s | 704.093us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 359.830s | 7011.547us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 359.830s | 7011.547us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 359.830s | 7011.547us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 359.830s | 7011.547us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1102.020s | 18402.408us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 45.270s | 1131.767us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 108.530s | 6239.771us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 108.530s | 6239.771us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 359.830s | 7011.547us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 84.920s | 3119.691us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 84.920s | 3119.691us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 84.920s | 3119.691us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 84.920s | 3119.691us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 49 | 50 | 98.00 | |||
| alert_handler_sig_int_fail | 82.930s | 5659.283us | 49 | 50 | 98.00 | |
| sec_cm_lpg_intersig_mubi | 48 | 50 | 96.00 | |||
| alert_handler_lpg | 3467.440s | 549761.953us | 48 | 50 | 96.00 | |
| sec_cm_esc_intersig_diff | 49 | 50 | 98.00 | |||
| alert_handler_sig_int_fail | 82.930s | 5659.283us | 49 | 50 | 98.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 24 | 25 | 96.00 | |||
| alert_handler_entropy | 3433.520s | 609284.239us | 24 | 25 | 96.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 24 | 25 | 96.00 | |||
| alert_handler_entropy | 3433.520s | 609284.239us | 24 | 25 | 96.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 45.270s | 1131.767us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 45.270s | 1131.767us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 45.270s | 1131.767us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 45.270s | 1131.767us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 45.270s | 1131.767us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 45.270s | 1131.767us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 45.270s | 1131.767us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 45.270s | 1131.767us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 45.270s | 1131.767us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 2 | 10 | 20.00 | |||
| alert_handler_stress_all_with_rand_reset | 373.720s | 16327.460us | 2 | 10 | 20.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:482) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 23 test runs | |||
| alert_handler_ping_timeout | 72412653019641700337907239955874071605127337278666095070254990951984426065266 | 111 |
UVM_INFO @ 21298781659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 13592657165508575022342648440609031899498040872388911093136898518922463636428 | 99 |
UVM_INFO @ 10502992003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 21120741812594947012540173193864135151751615987298212445780748808455385072554 | 124 |
UVM_INFO @ 76122868510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 43897549042462702077624195241479829365098695094745505473418724442081528428553 | 90 |
UVM_INFO @ 2497171520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 13528659348311533541160142749137202799996441676475379099146138246527553532915 | 99 |
UVM_INFO @ 3679311739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 96842268783232047842100493020891335501743235712306593654708832083100397892894 | 142 |
UVM_INFO @ 8102302225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 47381955276791777349638610757354496539358570144154745881505889750718557263731 | 144 |
UVM_INFO @ 7066657000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 16500719593262268843303670835021662895752034838957773311733540558929361598387 | 114 |
UVM_INFO @ 10220031640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 35102647168957320323039619401280189113602831370839904835247328133689889861175 | 90 |
UVM_INFO @ 2633645432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 100184846987622035007277828615983005822940079151715412610949438398210487150512 | 99 |
UVM_INFO @ 9023213228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 49798867594304390538084897274303467356903819141499228867310115185349650798586 | 121 |
UVM_INFO @ 3683936584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 87863850947800712959183635353080008940718211189172928016413345433831557835449 | 126 |
UVM_INFO @ 28063343675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 44265603976658417784612909881685703566047690272036821681233747275841716719436 | 90 |
UVM_INFO @ 4016269946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 4560361715174733898693055265404834251829247513352498785566198379442406970552 | 96 |
UVM_INFO @ 10361566408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 78817811709065592930192068594328892254087722835025757193221591849990824634393 | 90 |
UVM_INFO @ 1371024538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 16121374013311960256983866137759654842354104508832296764635708112237835674185 | 140 |
UVM_INFO @ 16676630150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 4989762110487663143983801571311620050878551692380748449697053186540195053414 | 110 |
UVM_INFO @ 2849736319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 90987076342253222352596683014331797418563138250507476970396760662556115086414 | 121 |
UVM_INFO @ 10805287577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 68193303755215634768298876395908840524148044775120301509970006226486892174574 | 135 |
UVM_INFO @ 19497588439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 12936391674968821264396567795932792451538895035783551066958590287736336325482 | 108 |
UVM_INFO @ 5244634349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 110764521531090320849591010182477191749900639371426621113306798228612751029103 | 107 |
UVM_INFO @ 3448859232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 112146383267316100220542872708097714331676836056806576304629043378391386039741 | 108 |
UVM_INFO @ 6464567777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 53691648709414466600282640848071790100841790385311302564805708611079854736063 | 117 |
UVM_INFO @ 10494058174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 21 test runs | |||
| alert_handler_entropy_stress | 109201760180134483271983457556555184709333715331713707666330660696530136067312 | 194 |
UVM_INFO @ 654794496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 70073618942276620630827086369124365848263553260153077230379062793098516909654 | 122 |
UVM_INFO @ 885096842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 84832164836058834801515332751105201355800228438759904911816783220197060487310 | 216 |
UVM_INFO @ 181852146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 105027538019302129750225967571757940825538800176558648823758604154953244171311 | 202 |
UVM_INFO @ 652125237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy | 22381625905308679046672118633911652910391955686984844678280987412611359406389 | 86 |
UVM_INFO @ 55516979708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 1140318853824690994035095065429417104220622098528151846979354404674534023644 | 182 |
UVM_INFO @ 586599947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 93308776979164997086947750211863294911887826277016500911638068971148803922112 | 212 |
UVM_INFO @ 800956361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 27694916526367016526218399911044511441850508362839765978093781851044541155275 | 214 |
UVM_INFO @ 2940327211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 75605251747231212773741861930355667914227532889452846319659043255921155012457 | 216 |
UVM_INFO @ 1450040462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 110621129923324064893110727694884685236206810741173159590594071953188544783404 | 210 |
UVM_INFO @ 2009692535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 111832748827245912998446687523579977268211805813441742140339740141149073375654 | 172 |
UVM_INFO @ 254589417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 58141498852116370967987338919645299409267401828596538736737080693345148285057 | 208 |
UVM_INFO @ 590381160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 31192753930597108387371784096849526596543656646771208166386957647709179759868 | 190 |
UVM_INFO @ 550497497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 104747291534311465684012728490377343006849601701705563412034410860111121542696 | 178 |
UVM_INFO @ 1759414625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 31208088613783865217664500721689941988024607022939193908835963935154504299225 | 214 |
UVM_INFO @ 715734365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 106575818644035907001045631704734916625619251923470787019458286422596134235160 | 208 |
UVM_INFO @ 102204818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 92960357006665778866010350868984011689377619353778704414936698674796602366732 | 218 |
UVM_INFO @ 438602274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 111389346144946679615922270729656542410680485883361666704711745348080444255521 | 160 |
UVM_INFO @ 870217588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 97202097774655365404093829633157882395666219168878853185575356134764863949524 | 198 |
UVM_INFO @ 713896417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 91905350541220056723674162494314886882542352928202036413605189028558831534883 | 214 |
UVM_INFO @ 1148401353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 35410840158143482856617899180430231731306143441752230907842042821500584922230 | 204 |
UVM_INFO @ 102399236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:604) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 8 test runs | |||
| alert_handler_ping_timeout | 78502914851755084641646826705805192145600725714474217282802833593593346015934 | 86 |
UVM_INFO @ 1638661608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 42061997371767240076551075872523225045169031610369221070704902908027630439426 | 86 |
UVM_INFO @ 535608175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 99070050470546497787958874997073004317317636492443253571984809758203855647100 | 86 |
UVM_INFO @ 826704660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 45907369854678363274569852798187518215523607462346077105440469950547963286679 | 86 |
UVM_INFO @ 1295320131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 69125446432327489902203641478222303796252293827932075388809625816237660466906 | 86 |
UVM_INFO @ 1342284247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_lpg | 18198401112401475919230487371278631829891421158616206333950056180784558548004 | 86 |
UVM_INFO @ 20862198170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 36094847089314543487531403417396516194927321821737503414674798103672442619083 | 89 |
UVM_INFO @ 2297270013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_lpg | 39957245615740362786340675636920992482782386498247673805990414886046603751502 | 86 |
UVM_INFO @ 2036182837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 8 test runs | |||
| alert_handler_stress_all_with_rand_reset | 78863119628123854285090871515580341584149279697611931022996907999718840374657 | 113 |
UVM_INFO @ 5176612169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 2096632424000692973844865882165580381836768017332095544268137278654198219586 | 94 |
UVM_INFO @ 1185140322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 35159060204849383575239841577918107681480881441095800506695317736763533648789 | 107 |
UVM_INFO @ 309527475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 22575625779005563885281788282336807400714591173943645338034237263800340399918 | 112 |
UVM_INFO @ 1518862231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 106804252332719442820535487844457383712739693663469881431203723648972942841466 | 88 |
UVM_INFO @ 281941004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 113222687521732027207501985620133149539174684645224902590337019663946030264462 | 98 |
UVM_INFO @ 1095180848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 2588963111407848916827189930259920601110504782079279397515208680968193005111 | 145 |
UVM_INFO @ 7774176512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 72240075158058550653943296059362462846368645954612583043054429601584255829169 | 89 |
UVM_INFO @ 173079498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail) | 1 test run | |||
| alert_handler_sig_int_fail | 51625992322548702193421721263291443865249988513552651865680613808200024890508 | 90 |
UVM_INFO @ 1020775578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classa_accum_cnt | 1 test run | |||
| alert_handler_lpg_stub_clk | 126272506621649755879417199382262035555544255377420331474281745030629297828 | 86 |
UVM_INFO @ 5567862392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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|