| V1 |
|
0.00% |
| V2 |
|
0.00% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| unmapped |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_example_tests | 0 | 12 | 0.00 | |||
| chip_sw_example_flash | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_example_rom | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_example_manufacturer | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_example_concurrency | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| chip_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 5 | 0.00 | |||
| chip_csr_rw | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| chip_csr_bit_bash | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| chip_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 5 | 0.00 | |||
| chip_csr_mem_rw_with_rand_reset | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 6 | 0.00 | |||
| chip_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_csr_rw | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| xbar_smoke | 0 | 50 | 0.00 | |||
| xbar_smoke | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| chip_sw_gpio_out | 0 | 3 | 0.00 | |||
| chip_sw_gpio | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_gpio_in | 0 | 3 | 0.00 | |||
| chip_sw_gpio | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_gpio_irq | 0 | 3 | 0.00 | |||
| chip_sw_gpio | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_uart_tx_rx | 0 | 5 | 0.00 | |||
| chip_sw_uart_tx_rx | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_sw_uart_rx_overflow | 0 | 20 | 0.00 | |||
| chip_sw_uart_tx_rx | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_sw_uart_tx_rx_idx1 | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_sw_uart_tx_rx_idx2 | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_sw_uart_tx_rx_idx3 | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_sw_uart_baud_rate | 0 | 20 | 0.00 | |||
| chip_sw_uart_rand_baudrate | 0.000s | 0.000us | 0 | 20 | 0.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq | 0 | 10 | 0.00 | |||
| chip_sw_uart_tx_rx_alt_clk_freq | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_pin_mux | 0 | 10 | 0.00 | |||
| chip_padctrl_attributes | 0.000s | 0.000us | 0 | 10 | 0.00 | |
| chip_padctrl_attributes | 0 | 10 | 0.00 | |||
| chip_padctrl_attributes | 0.000s | 0.000us | 0 | 10 | 0.00 | |
| chip_sw_sleep_pin_mio_dio_val | 0 | 3 | 0.00 | |||
| chip_sw_sleep_pin_mio_dio_val | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sleep_pin_wake | 0 | 3 | 0.00 | |||
| chip_sw_sleep_pin_wake | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sleep_pin_retention | 0 | 3 | 0.00 | |||
| chip_sw_sleep_pin_retention | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_tap_strap_sampling | 0 | 20 | 0.00 | |||
| chip_tap_straps_dev | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_tap_straps_testunlock0 | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_tap_straps_rma | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_tap_straps_prod | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_sw_data_integrity | 0 | 6 | 0.00 | |||
| chip_sw_data_integrity_escalation | 0.000s | 0.000us | 0 | 6 | 0.00 | |
| chip_sw_instruction_integrity | 0 | 6 | 0.00 | |||
| chip_sw_data_integrity_escalation | 0.000s | 0.000us | 0 | 6 | 0.00 | |
| chip_sw_ast_clk_outputs | 0 | 3 | 0.00 | |||
| chip_sw_ast_clk_outputs | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_ast_clk_rst_inputs | 0 | 3 | 0.00 | |||
| chip_sw_ast_clk_rst_inputs | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_ast_sys_clk_jitter | 0 | 30 | 0.00 | |||
| chip_sw_flash_ctrl_ops_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_edn_entropy_reqs_jitter | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_jitter | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_ast_usb_clk_calib | 0 | 1 | 0.00 | |||
| chip_sw_usb_ast_clk_calib | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sensor_ctrl_ast_alerts | 0 | 8 | 0.00 | |||
| chip_sw_sensor_ctrl_alert | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sensor_ctrl_ast_status | 0 | 3 | 0.00 | |||
| chip_sw_sensor_ctrl_status | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_smoketest | 0 | 48 | 0.00 | |||
| chip_sw_aes_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aon_timer_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_csrng_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_entropy_src_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_gpio_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_hmac_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_kmac_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_usbdev_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rv_plic_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rv_timer_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rstmgr_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sram_ctrl_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_uart_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otp_smoketest | 0 | 3 | 0.00 | |||
| chip_sw_otp_ctrl_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rom_functests | 0 | 3 | 0.00 | |||
| rom_keymgr_functest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_boot | 0 | 3 | 0.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_secure_boot | 0 | 3 | 0.00 | |||
| rom_e2e_smoke | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rom_raw_unlock | 0 | 3 | 0.00 | |||
| rom_raw_unlock | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_power_idle_load | 0 | 3 | 0.00 | |||
| chip_sw_power_idle_load | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_power_sleep_load | 0 | 3 | 0.00 | |||
| chip_sw_power_sleep_load | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_exit_test_unlocked_bootstrap | 0 | 3 | 0.00 | |||
| chip_sw_exit_test_unlocked_bootstrap | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_inject_scramble_seed | 0 | 3 | 0.00 | |||
| chip_sw_inject_scramble_seed | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| tl_d_oob_addr_access | 0 | 30 | 0.00 | |||
| chip_tl_errors | 0.000s | 0.000us | 0 | 30 | 0.00 | |
| tl_d_illegal_access | 0 | 30 | 0.00 | |||
| chip_tl_errors | 0.000s | 0.000us | 0 | 30 | 0.00 | |
| tl_d_outstanding_access | 0 | 12 | 0.00 | |||
| chip_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_same_csr_outstanding | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_csr_rw | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| tl_d_partial_access | 0 | 12 | 0.00 | |||
| chip_csr_aliasing | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_same_csr_outstanding | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_csr_hw_reset | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_csr_rw | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| xbar_base_random_sequence | 0 | 50 | 0.00 | |||
| xbar_random | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_random_delay | 0 | 300 | 0.00 | |||
| xbar_smoke_zero_delays | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_smoke_large_delays | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_smoke_slow_rsp | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_random_zero_delays | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_random_large_delays | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_random_slow_rsp | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_unmapped_address | 0 | 100 | 0.00 | |||
| xbar_unmapped_addr | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_error_and_unmapped_addr | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_error_cases | 0 | 100 | 0.00 | |||
| xbar_error_random | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_error_and_unmapped_addr | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_all_access_same_device | 0 | 100 | 0.00 | |||
| xbar_access_same_device | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_access_same_device_slow_rsp | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_all_hosts_use_same_source_id | 0 | 50 | 0.00 | |||
| xbar_same_source | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_stress_all | 0 | 100 | 0.00 | |||
| xbar_stress_all | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_stress_all_with_error | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_stress_with_reset | 0 | 100 | 0.00 | |||
| xbar_stress_all_with_rand_reset | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| xbar_stress_all_with_reset_error | 0.000s | 0.000us | 0 | 50 | 0.00 | |
| rom_e2e_smoke | 0 | 3 | 0.00 | |||
| rom_e2e_smoke | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_shutdown_output | 0 | 3 | 0.00 | |||
| rom_e2e_shutdown_output | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_shutdown_exception_c | 0 | 3 | 0.00 | |||
| rom_e2e_shutdown_exception_c | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_boot_policy_valid | 0 | 15 | 0.00 | |||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always | 0 | 15 | 0.00 | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init | 0 | 15 | 0.00 | |||
| rom_e2e_asm_init_test_unlocked0 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_dev | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_prod | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_prod_end | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_rma | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_keymgr_init | 0 | 9 | 0.00 | |||
| rom_e2e_keymgr_init_rom_ext_meas | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_keymgr_init_rom_ext_no_meas | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_static_critical | 0 | 3 | 0.00 | |||
| rom_e2e_static_critical | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_adc_ctrl_debug_cable_irq | 0 | 3 | 0.00 | |||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0 | 3 | 0.00 | |||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aes_enc | 0 | 6 | 0.00 | |||
| chip_sw_aes_enc | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aes_entropy | 0 | 3 | 0.00 | |||
| chip_sw_aes_entropy | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aes_idle | 0 | 3 | 0.00 | |||
| chip_sw_aes_idle | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aes_sideload | 0 | 3 | 0.00 | |||
| chip_sw_keymgr_sideload_aes | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_alerts | 0 | 3 | 0.00 | |||
| chip_sw_alert_test | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_escalations | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_escalation | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_all_escalation_resets | 0 | 100 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 100 | 0.00 | |
| chip_sw_alert_handler_irqs | 0 | 9 | 0.00 | |||
| chip_plic_all_irqs_0 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_plic_all_irqs_10 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_plic_all_irqs_20 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_entropy | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_entropy | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_crashdump | 0 | 3 | 0.00 | |||
| chip_sw_rstmgr_alert_info | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_ping_timeout | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_ping_timeout | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 90 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0.000s | 0.000us | 0 | 90 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_lpg_clock_off | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_lpg_reset_toggle | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_ping_ok | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_ping_ok | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aon_timer_wakeup_irq | 0 | 3 | 0.00 | |||
| chip_sw_aon_timer_irq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aon_timer_sleep_wakeup | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aon_timer_wdog_bark_irq | 0 | 3 | 0.00 | |||
| chip_sw_aon_timer_irq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 0 | 3 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_bite_reset | 0 | 3 | 0.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 0 | 5 | 0.00 | |||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_sw_aon_timer_wdog_lc_escalate | 0 | 3 | 0.00 | |||
| chip_sw_aon_timer_wdog_lc_escalate | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_idle_trans | 0 | 12 | 0.00 | |||
| chip_sw_otbn_randomness | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aes_idle | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_hmac_enc_idle | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_kmac_idle | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_off_trans | 0 | 12 | 0.00 | |||
| chip_sw_clkmgr_off_aes_trans | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_off_hmac_trans | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_off_kmac_trans | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_off_otbn_trans | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_off_peri | 0 | 3 | 0.00 | |||
| chip_sw_clkmgr_off_peri | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_div | 0 | 21 | 0.00 | |||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_ast_clk_outputs | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_lc | 0 | 3 | 0.00 | |||
| chip_sw_clkmgr_external_clk_src_for_lc | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw | 0 | 6 | 0.00 | |||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_jitter | 0 | 30 | 0.00 | |||
| chip_sw_flash_ctrl_ops_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aes_enc_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_edn_entropy_reqs_jitter | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_jitter | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_extended_range | 0 | 33 | 0.00 | |||
| chip_sw_clkmgr_jitter_reduced_freq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aes_enc_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_hmac_enc_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_init_reduced_freq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_csrng_edn_concurrency_reduced_freq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_deep_sleep_frequency | 0 | 3 | 0.00 | |||
| chip_sw_ast_clk_outputs | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_sleep_frequency | 0 | 3 | 0.00 | |||
| chip_sw_clkmgr_sleep_frequency | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_reset_frequency | 0 | 3 | 0.00 | |||
| chip_sw_clkmgr_reset_frequency | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_escalation_reset | 0 | 100 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 100 | 0.00 | |
| chip_sw_clkmgr_alert_handler_clock_enables | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_csrng_edn_cmd | 0 | 3 | 0.00 | |||
| chip_sw_entropy_src_csrng | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_csrng_fuse_en_sw_app_read | 0 | 3 | 0.00 | |||
| chip_sw_csrng_fuse_en_sw_app_read_test | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_csrng_lc_hw_debug_en | 0 | 3 | 0.00 | |||
| chip_sw_csrng_lc_hw_debug_en_test | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_csrng_known_answer_tests | 0 | 3 | 0.00 | |||
| chip_sw_csrng_kat_test | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_edn_entropy_reqs | 0 | 16 | 0.00 | |||
| chip_sw_csrng_edn_concurrency | 0.000s | 0.000us | 0 | 10 | 0.00 | |
| chip_sw_entropy_src_ast_rng_req | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_edn_entropy_reqs | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_entropy_src_ast_rng_req | 0 | 3 | 0.00 | |||
| chip_sw_entropy_src_ast_rng_req | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_entropy_src_csrng | 0 | 3 | 0.00 | |||
| chip_sw_entropy_src_csrng | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_entropy_src_known_answer_tests | 0 | 3 | 0.00 | |||
| chip_sw_entropy_src_kat_test | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_init | 0 | 3 | 0.00 | |||
| chip_sw_flash_init | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_host_access | 0 | 6 | 0.00 | |||
| chip_sw_flash_ctrl_access | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_ops | 0 | 6 | 0.00 | |||
| chip_sw_flash_ctrl_ops | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_ops_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_rma_unlocked | 0 | 3 | 0.00 | |||
| chip_sw_flash_rma_unlocked | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_scramble | 0 | 3 | 0.00 | |||
| chip_sw_flash_init | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_idle_low_power | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_idle_low_power | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_keymgr_seeds | 0 | 3 | 0.00 | |||
| chip_sw_keymgr_key_derivation | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_creator_seed_sw_rw_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_creator_seed_wipe_on_rma | 0 | 3 | 0.00 | |||
| chip_sw_flash_rma_unlocked | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_owner_seed_sw_rw_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_iso_part_sw_rd_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_iso_part_sw_wr_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_seed_hw_rd_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_escalate_en | 0 | 100 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 100 | 0.00 | |
| chip_sw_flash_prim_tl_access | 0 | 3 | 0.00 | |||
| chip_prim_tl_access | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_clock_freqs | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_clock_freqs | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_escalation_reset | 0 | 3 | 0.00 | |||
| chip_sw_flash_crash_alert | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_write_clear | 0 | 3 | 0.00 | |||
| chip_sw_flash_crash_alert | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_hmac_enc | 0 | 6 | 0.00 | |||
| chip_sw_hmac_enc | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_hmac_enc_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_hmac_idle | 0 | 3 | 0.00 | |||
| chip_sw_hmac_enc_idle | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_hmac_all_configurations | 0 | 3 | 0.00 | |||
| chip_sw_hmac_oneshot | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_hmac_multistream_mode | 0 | 3 | 0.00 | |||
| chip_sw_hmac_multistream | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_i2c_host_tx_rx | 0 | 9 | 0.00 | |||
| chip_sw_i2c_host_tx_rx | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_i2c_host_tx_rx_idx1 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_i2c_host_tx_rx_idx2 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_i2c_device_tx_rx | 0 | 3 | 0.00 | |||
| chip_sw_i2c_device_tx_rx | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_keymgr_key_derivation | 0 | 6 | 0.00 | |||
| chip_sw_keymgr_key_derivation | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_keymgr_sideload_kmac | 0 | 3 | 0.00 | |||
| chip_sw_keymgr_sideload_kmac | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_keymgr_sideload_aes | 0 | 3 | 0.00 | |||
| chip_sw_keymgr_sideload_aes | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_keymgr_sideload_otbn | 0 | 3 | 0.00 | |||
| chip_sw_keymgr_sideload_otbn | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_kmac_enc | 0 | 9 | 0.00 | |||
| chip_sw_kmac_mode_cshake | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_kmac_mode_kmac | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_kmac_app_keymgr | 0 | 3 | 0.00 | |||
| chip_sw_keymgr_key_derivation | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_kmac_app_lc | 0 | 15 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 15 | 0.00 | |
| chip_sw_kmac_app_rom | 0 | 3 | 0.00 | |||
| chip_sw_kmac_app_rom | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_kmac_entropy | 0 | 3 | 0.00 | |||
| chip_sw_kmac_entropy | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_kmac_idle | 0 | 3 | 0.00 | |||
| chip_sw_kmac_idle | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_alert_handler_escalation | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_escalation | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_jtag_access | 0 | 15 | 0.00 | |||
| chip_tap_straps_dev | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_tap_straps_rma | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_tap_straps_prod | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_sw_lc_ctrl_otp_hw_cfg0 | 0 | 3 | 0.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_init | 0 | 15 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 15 | 0.00 | |
| chip_sw_lc_ctrl_transitions | 0 | 15 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 15 | 0.00 | |
| chip_sw_lc_ctrl_kmac_req | 0 | 15 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 15 | 0.00 | |
| chip_sw_lc_ctrl_key_div | 0 | 3 | 0.00 | |||
| chip_sw_keymgr_key_derivation_prod | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_broadcast | 0 | 84 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_rma_unlocked | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 15 | 0.00 | |
| chip_sw_keymgr_key_derivation | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rom_ctrl_integrity_check | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sram_ctrl_execution_main | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_prim_tl_access | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_lc | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_tap_straps_dev | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_tap_straps_rma | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_tap_straps_prod | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_rv_dm_lc_disabled | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_lc_scrap | 0 | 6 | 0.00 | |||
| chip_sw_lc_ctrl_rma_to_scrap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_raw_to_scrap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_test_locked0_to_scrap | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_lc_ctrl_rand_to_scrap | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_lc_test_locked | 0 | 6 | 0.00 | |||
| chip_sw_lc_walkthrough_testunlocks | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_rv_dm_lc_disabled | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough | 0 | 15 | 0.00 | |||
| chip_sw_lc_walkthrough_dev | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_prod | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_prodend | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_rma | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock | 0 | 9 | 0.00 | |||
| chip_sw_lc_ctrl_volatile_raw_unlock | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| rom_volatile_raw_unlock | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_op | 0 | 6 | 0.00 | |||
| chip_sw_otbn_ecdsa_op_irq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_rnd_entropy | 0 | 3 | 0.00 | |||
| chip_sw_otbn_randomness | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_urnd_entropy | 0 | 3 | 0.00 | |||
| chip_sw_otbn_randomness | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_idle | 0 | 3 | 0.00 | |||
| chip_sw_otbn_randomness | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_mem_scramble | 0 | 3 | 0.00 | |||
| chip_sw_otbn_mem_scramble | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_otp_ctrl_init | 0 | 15 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 15 | 0.00 | |
| chip_sw_otp_ctrl_keys | 0 | 15 | 0.00 | |||
| chip_sw_flash_init | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_mem_scramble | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_keymgr_key_derivation | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_entropy | 0 | 15 | 0.00 | |||
| chip_sw_flash_init | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_mem_scramble | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_keymgr_key_derivation | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_program | 0 | 15 | 0.00 | |||
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 15 | 0.00 | |
| chip_sw_otp_ctrl_program_error | 0 | 3 | 0.00 | |||
| chip_sw_lc_ctrl_program_error | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_hw_cfg0 | 0 | 3 | 0.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals | 0 | 30 | 0.00 | |||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_transition | 0.000s | 0.000us | 0 | 15 | 0.00 | |
| chip_prim_tl_access | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otp_prim_tl_access | 0 | 3 | 0.00 | |||
| chip_prim_tl_access | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_dai_lock | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_dai_lock | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_pwrmgr_external_full_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_por_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_por_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_normal_sleep_por_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_normal_sleep_por_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 0 | 6 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_wdog_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_wdog_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_main_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_main_power_glitch_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_sysrst_ctrl_reset | 0 | 6 | 0.00 | |||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_all_reset_reqs | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_b2b_sleep_reset_req | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_b2b_sleep_reset_req | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_sleep_disabled | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_sleep_disabled | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_escalation_reset | 0 | 100 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 100 | 0.00 | |
| chip_sw_rom_access | 0 | 3 | 0.00 | |||
| chip_sw_rom_ctrl_integrity_check | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rom_ctrl_integrity_check | 0 | 3 | 0.00 | |||
| chip_sw_rom_ctrl_integrity_check | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rstmgr_non_sys_reset_info | 0 | 12 | 0.00 | |||
| chip_sw_pwrmgr_all_reset_reqs | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_wdog_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rstmgr_sys_reset_info | 0 | 3 | 0.00 | |||
| chip_rv_dm_ndm_reset_req | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rstmgr_cpu_info | 0 | 3 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rstmgr_sw_req_reset | 0 | 3 | 0.00 | |||
| chip_sw_rstmgr_sw_req | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rstmgr_alert_info | 0 | 3 | 0.00 | |||
| chip_sw_rstmgr_alert_info | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rstmgr_sw_rst | 0 | 3 | 0.00 | |||
| chip_sw_rstmgr_sw_rst | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rstmgr_escalation_reset | 0 | 100 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 100 | 0.00 | |
| chip_sw_rstmgr_alert_handler_reset_enables | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_nmi_irq | 0 | 3 | 0.00 | |||
| chip_sw_rv_core_ibex_nmi_irq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rv_core_ibex_rnd | 0 | 3 | 0.00 | |||
| chip_sw_rv_core_ibex_rnd | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rv_core_ibex_address_translation | 0 | 3 | 0.00 | |||
| chip_sw_rv_core_ibex_address_translation | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rv_core_ibex_icache_scrambled_access | 0 | 3 | 0.00 | |||
| chip_sw_rv_core_ibex_icache_invalidate | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rv_core_ibex_fault_dump | 0 | 3 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rv_core_ibex_double_fault | 0 | 3 | 0.00 | |||
| chip_sw_rstmgr_cpu_info | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rv_core_ibex_mcounteren_writable | 0 | 3 | 0.00 | |||
| chip_sw_rv_core_ibex_mcounteren_writable | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_jtag_csr_rw | 0 | 3 | 0.00 | |||
| chip_jtag_csr_rw | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_jtag_mem_access | 0 | 3 | 0.00 | |||
| chip_jtag_mem_access | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_rv_dm_ndm_reset_req | 0 | 3 | 0.00 | |||
| chip_rv_dm_ndm_reset_req | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 3 | 0.00 | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_rv_dm_access_after_wakeup | 0 | 3 | 0.00 | |||
| chip_sw_rv_dm_access_after_wakeup | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rv_dm_jtag_tap_sel | 0 | 5 | 0.00 | |||
| chip_tap_straps_rma | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | |||
| chip_rv_dm_lc_disabled | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_plic_all_irqs | 0 | 9 | 0.00 | |||
| chip_plic_all_irqs_0 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_plic_all_irqs_10 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_plic_all_irqs_20 | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_plic_sw_irq | 0 | 3 | 0.00 | |||
| chip_sw_plic_sw_irq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_timer | 0 | 3 | 0.00 | |||
| chip_sw_rv_timer_irq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_flash_mode | 0 | 3 | 0.00 | |||
| rom_e2e_smoke | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_pass_through | 0 | 3 | 0.00 | |||
| chip_sw_spi_device_pass_through | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_pass_through_collision | 0 | 3 | 0.00 | |||
| chip_sw_spi_device_pass_through_collision | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_tpm | 0 | 3 | 0.00 | |||
| chip_sw_spi_device_tpm | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_spi_host_tx_rx | 0 | 3 | 0.00 | |||
| chip_sw_spi_host_tx_rx | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sram_scrambled_access | 0 | 6 | 0.00 | |||
| chip_sw_sram_ctrl_scrambled_access | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sleep_sram_ret_contents | 0 | 6 | 0.00 | |||
| chip_sw_sleep_sram_ret_contents_no_scramble | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sleep_sram_ret_contents_scramble | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sram_execution | 0 | 3 | 0.00 | |||
| chip_sw_sram_ctrl_execution_main | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sram_lc_escalation | 0 | 106 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 100 | 0.00 | |
| chip_sw_data_integrity_escalation | 0.000s | 0.000us | 0 | 6 | 0.00 | |
| chip_sw_sysrst_ctrl_reset | 0 | 6 | 0.00 | |||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sysrst_ctrl_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sysrst_ctrl_inputs | 0 | 3 | 0.00 | |||
| chip_sw_sysrst_ctrl_inputs | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sysrst_ctrl_outputs | 0 | 3 | 0.00 | |||
| chip_sw_sysrst_ctrl_outputs | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sysrst_ctrl_in_irq | 0 | 3 | 0.00 | |||
| chip_sw_sysrst_ctrl_in_irq | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sysrst_ctrl_sleep_wakeup | 0 | 3 | 0.00 | |||
| chip_sw_sysrst_ctrl_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sysrst_ctrl_sleep_reset | 0 | 3 | 0.00 | |||
| chip_sw_sysrst_ctrl_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sysrst_ctrl_ec_rst_l | 0 | 3 | 0.00 | |||
| chip_sw_sysrst_ctrl_ec_rst_l | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sysrst_ctrl_flash_wp_l | 0 | 3 | 0.00 | |||
| chip_sw_sysrst_ctrl_ec_rst_l | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 0 | 6 | 0.00 | |||
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_usbdev_vbus | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_vbus | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_usbdev_pullup | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_pullup | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_usbdev_aon_pullup | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_aon_pullup | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_usbdev_setup_rx | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_setuprx | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_usbdev_config_host | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_config_host | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_usbdev_pincfg | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_pincfg | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_usbdev_tx_rx | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_dpi | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_usbdev_toggle_restore | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_toggle_restore | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_aes_masking_off | 0 | 3 | 0.00 | |||
| chip_sw_aes_masking_off | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rv_core_ibex_lockstep_glitch | 0 | 3 | 0.00 | |||
| chip_sw_rv_core_ibex_lockstep_glitch | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_coremark | 0 | 1 | 0.00 | |||
| chip_sw_coremark | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_power_max_load | 0 | 3 | 0.00 | |||
| chip_sw_power_virus | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_inject_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_self_hash | 0 | 3 | 0.00 | |||
| rom_e2e_self_hash | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_jitter_cycle_measurements | 0 | 3 | 0.00 | |||
| chip_sw_clkmgr_jitter_frequency | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_edn_boot_mode | 0 | 3 | 0.00 | |||
| chip_sw_edn_boot_mode | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_edn_auto_mode | 0 | 3 | 0.00 | |||
| chip_sw_edn_auto_mode | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_edn_sw_mode | 0 | 3 | 0.00 | |||
| chip_sw_edn_sw_mode | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_edn_kat | 0 | 3 | 0.00 | |||
| chip_sw_edn_kat | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_memory_protection | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_mem_protection | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_escalation | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_escalation | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_sensor_ctrl_deep_sleep_wake_up | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_all_resets | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_all_reset_reqs | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_rv_dm_perform_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_access_after_hw_reset | 0 | 3 | 0.00 | |||
| chip_sw_rv_dm_access_after_escalation_reset | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_plic_alerts | 0 | 100 | 0.00 | |||
| chip_sw_all_escalation_resets | 0.000s | 0.000us | 0 | 100 | 0.00 | |
| tick_configuration | 0 | 3 | 0.00 | |||
| chip_sw_rv_timer_systick_test | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| counter_wrap | 0 | 3 | 0.00 | |||
| chip_sw_rv_timer_systick_test | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 3 | 0.00 | |||
| chip_sw_spi_device_pinmux_sleep_retention | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_uart_watermarks | 0 | 5 | 0.00 | |||
| chip_sw_uart_tx_rx | 0.000s | 0.000us | 0 | 5 | 0.00 | |
| chip_sw_usbdev_stream | 0 | 1 | 0.00 | |||
| chip_sw_usbdev_stream | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 0 | 31 | 0.00 | |||
| chip_sival_flash_info_access | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_rot_auth_config | 0.000s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_descrambling | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_lowpower_cancel | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_sleep_wake_5_bug | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_write_clear | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_scrambling_smoketest | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| ate_bootstrap_flash_erase | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| ate_bootstrap_one_frame | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| ate_bootstrap_disjoint | 0.000s | 0.000us | 0 | 3 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job cancelled because one of its dependencies failed or was killed. | 2000 test runs | |||
| chip_csr_bit_bash | 26677137260381667494697215489128869276816230053204664583590851048951458327151 | None | ||
| chip_csr_aliasing | 45825579572608611795108230081889694911085547466771829128606771856104893807884 | None | ||
| chip_same_csr_outstanding | 3445313115525696016157391668390466101147940553957494617253557957460157262832 | None | ||
| chip_sw_example_flash | 20880270222657980180136254961881098406033965115205378594088477507489378181642 | None | ||
| chip_sw_example_rom | 86758809680871372552019095885694742460228817543689766275814018596902650270688 | None | ||
| chip_sw_example_manufacturer | 64582639422136238410228728812950298290357233101707488526702243191296690779222 | None | ||
| chip_sw_example_concurrency | 74785881148947591343939007579168522767056921777752344541559576155851155763271 | None | ||
| chip_sival_flash_info_access | 104176501558767165663833446797561039790067654663692700003455825648988335449256 | None | ||
| chip_sw_all_escalation_resets | 8467631808158720140126847331285130380440839714722285819804616144717640805929 | None | ||
| chip_sw_rstmgr_rst_cnsty_escalation | 90220848250274005516491422079101278667725160499631610367980189656700568060816 | None | ||
| chip_sw_data_integrity_escalation | 76642864129918450562448386654218414951168589838763627079173923429815684150996 | None | ||
| chip_sw_sleep_pin_mio_dio_val | 14156845950028886042014725171956797279217198252507476729561121950285631012703 | None | ||
| chip_sw_sleep_pin_wake | 92734653960522486031585182933034845060314719528607687525542962163561382433249 | None | ||
| chip_sw_sleep_pin_retention | 45115269876350754672272589941473846935448324319922549681245243805876899794799 | None | ||
| chip_sw_uart_tx_rx | 56555572496845988834076606976467071158973034786827919621990781262756966295291 | None | ||
| chip_sw_uart_tx_rx_idx1 | 4624147398098887506602450616261197497490903665189965929775994547935499353467 | None | ||
| chip_sw_uart_tx_rx_idx2 | 44973982350188146069915595040178153646538482679077755459587947804912586525854 | None | ||
| chip_sw_uart_tx_rx_idx3 | 9498074511815130323530156467775603724948814748154425484755830089885841587651 | None | ||
| chip_sw_uart_tx_rx_bootstrap | 114688801576861516087818097385669810964064291426477171071968861204101186946775 | None | ||
| chip_sw_usbdev_vbus | 20279417458784786341899745544217573204219078415650394631570081412933664853958 | None | ||
| chip_sw_usbdev_dpi | 30240179446930731076985241341779223497674002457427192006239077519811395502099 | None | ||
| chip_sw_usbdev_pullup | 44871817426841459197464067343733770271899397332219498822770843871141981634225 | None | ||
| chip_sw_usbdev_aon_pullup | 103454457675419468048365969112238665211091867447276905866804377726766354685051 | None | ||
| chip_sw_usbdev_setuprx | 6375953886577085319134646354641699134364467146035457197256006045980160309904 | None | ||
| chip_sw_usbdev_config_host | 23109964658552204067830630595207973700135249898082536343472671987893697628490 | None | ||
| chip_sw_usbdev_pincfg | 88412500896075691024337220690579402479969418791477265178017769981538390659870 | None | ||
| chip_sw_usbdev_stream | 79202394572668697864404188341330394303694793005293273614651091941764461657287 | None | ||
| chip_sw_usbdev_toggle_restore | 10685616681265775820282961501924486544374250117133838636289399056893822329244 | None | ||
| chip_sw_inject_scramble_seed | 91671921858779131664212640146013447274608993992843777385096569011979278765415 | None | ||
| chip_sw_exit_test_unlocked_bootstrap | 11885938821391871545594143189086945204233072250297936464464293067031283244976 | None | ||
| chip_sw_uart_rand_baudrate | 110629963179261669342417705887733225040841655692354507913105289818954710932538 | None | ||
| chip_sw_uart_tx_rx_alt_clk_freq | 93253462266610256746336158375397455462249193235277703600326445446381723087885 | None | ||
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 15602333761619064161970502540521159393503754667334935709017131708697677426922 | None | ||
| chip_sw_i2c_host_tx_rx | 23623467306340265037816511088955078085658380261561783638596840018923020217456 | None | ||
| chip_sw_i2c_host_tx_rx_idx1 | 33518925220440755875690898809575798103721781717637765665498691262651741554002 | None | ||
| chip_sw_i2c_host_tx_rx_idx2 | 78595124465353997654101798883161561266672902762626949190653007372888953045292 | None | ||
| chip_sw_i2c_device_tx_rx | 75743743970886003412514905136852187337340856005171944931695733472514536577022 | None | ||
| chip_sw_spi_device_tpm | 3139790584021852108640072491585848484569459091619555026057510488616243088150 | None | ||
| chip_sw_spi_host_tx_rx | 46670645143442010934790320261141900619451064495384578187975509698733458220605 | None | ||
| chip_sw_spi_device_pinmux_sleep_retention | 18634955121074536275059406553859541280773529101123926179838884215502231410721 | None | ||
| chip_sw_spi_device_pass_through | 59073520772912822955658582340180710436164413251102187608984375686787999661627 | None | ||
| chip_sw_spi_device_pass_through_collision | 36098125003915335038570316352065936504049627756483000721978520742729676965199 | None | ||
| chip_sw_gpio | 37999039432542820634608573399145456975226590625813163573679730672900855449741 | None | ||
| chip_sw_flash_ctrl_ops | 107921775553299689205215682354354083584870786611790133387503145690189581025597 | None | ||
| chip_sw_flash_ctrl_ops_jitter_en | 34870024200440491750062154492908227781414603111364386563377473179266654149983 | None | ||
| chip_sw_flash_ctrl_lc_rw_en | 45338928339929102953542341690180763982213345820581975108501314730548512698658 | None | ||
| chip_sw_flash_ctrl_access | 93408723040736613243300862110884286828807665588355119942275413130144512008027 | None | ||
| chip_sw_flash_ctrl_access_jitter_en | 113655868632971377671025244774164362080487619520679788258521999156404274197870 | None | ||
| chip_sw_flash_ctrl_idle_low_power | 20670633774730848433665737396073156842743205254527889651540472650073739650881 | None | ||
| chip_sw_flash_init | 30798723740479978550413347618151142109575520623630197380510807192791713398588 | None | ||
| chip_sw_flash_rma_unlocked | 50362300124338364213736577560845652396582311837884977047243105224376001244671 | None | ||
| chip_sw_flash_ctrl_clock_freqs | 110693042232943463988607378818621565135521965968206498281506752519391944480617 | None | ||
| chip_sw_kmac_entropy | 80016908355190331827272411999290630137990539895810960722601328113085628205015 | None | ||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 70195095483486416800429374064489424094506204571450745112984471802910935379438 | None | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 32912526472356414867061440384973513731472190901351167101647831162886155695032 | None | ||
| chip_sw_otp_ctrl_lc_signals_dev | 41962312243232092511788243729382600127233900117560902362137844300268077341165 | None | ||
| chip_sw_otp_ctrl_lc_signals_prod | 449856311487095995801753358674873261138356700969937885323423259457433764675 | None | ||
| chip_sw_otp_ctrl_lc_signals_rma | 30633954261574182341044172418758950815620495131415248148522803366400741889501 | None | ||
| chip_sw_otp_ctrl_escalation | 71045342429282027862559680294460707614855206381123468376182515357403122046065 | None | ||
| chip_sw_otp_ctrl_dai_lock | 94194346864212894884163340884221224782790822942414767050735023276935087400201 | None | ||
| chip_sw_otp_ctrl_rot_auth_config | 78965202262461718557883128417517094895145720365193226348860078964837706947283 | None | ||
| chip_sw_otp_ctrl_descrambling | 72404686740630348444266448350691301129681586399999584691385971199747781882606 | None | ||
| chip_sw_lc_ctrl_transition | 3372552939698565164793447963164987802565710161478692602112052626485357731077 | None | ||
| chip_sw_lc_ctrl_rma_to_scrap | 84187726711592585031778731928696318207725117512657897480127573736393364526446 | None | ||
| chip_sw_lc_ctrl_raw_to_scrap | 1471742718396888941764044171275263439262906384468603850656097811781373993127 | None | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 54714458690176460363579762923691172334042017487656683042750847908846729609602 | None | ||
| chip_sw_lc_ctrl_rand_to_scrap | 82382164737768898084190837836990354690386337373065751490732538117516065394922 | None | ||
| chip_sw_lc_walkthrough_dev | 31673458955272828976028648492180554705349588187292658158040098054903385398589 | None | ||
| chip_sw_lc_walkthrough_prod | 18432549331578594878782413308178902999835429517159369488477374551051875894586 | None | ||
| chip_sw_lc_walkthrough_prodend | 23765062114742341262133569751126893736083703351147977039337163723253816877075 | None | ||
| chip_sw_lc_ctrl_volatile_raw_unlock | 85375971861339459481241799537340794872882500778271934938898974692167348571559 | None | ||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 81125540216283804920077804594312073433938312332837181045114938534061471652520 | None | ||
| chip_sw_lc_walkthrough_rma | 27576869634313855187117019770690685928234046493228331426162356359379061238062 | None | ||
| chip_sw_lc_walkthrough_testunlocks | 53221110345339199852573152349741922839914063659204872650465008707134157282514 | None | ||
| chip_sw_rstmgr_sw_req | 37147084400648052903707151155309173359993238906702031981019554999931975737996 | None | ||
| chip_sw_rstmgr_sw_rst | 25984994978753001752957474932902919229101978279658887975196234017918520063574 | None | ||
| chip_sw_rstmgr_alert_info | 103520700712194204101834395875923378101883042713991503691307736415886052363552 | None | ||
| chip_sw_rstmgr_cpu_info | 24924051662136642369734466882870811595074838284194210064439315536317639721826 | None | ||
| chip_sw_pwrmgr_full_aon_reset | 6150977371826324980397795900180342314130205544432381872514731384271456269226 | None | ||
| chip_sw_pwrmgr_main_power_glitch_reset | 45265279444884457623594666757664799416659644815359740692522431634618381809712 | None | ||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 29216190268556377452876067830582992015537233420482989078779911520499673470989 | None | ||
| chip_sw_pwrmgr_all_reset_reqs | 63104384893133667879582550797883580697825093290612870484832087394137617134614 | None | ||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 25576628136222500804203489146730862463750152457010618979048274521668803133036 | None | ||
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 56229175054533323728707525972294675259175616353954529013820828911511762955840 | None | ||
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 86559414929249145985801209969641456151330092337025283430098368178652299332809 | None | ||
| chip_sw_pwrmgr_deep_sleep_por_reset | 7274820356292192911057139720099413911222409461181157510423978133735384152809 | None | ||
| chip_sw_pwrmgr_normal_sleep_por_reset | 81527633052274721743211220753288164483820759211939853064515819494673222204128 | None | ||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 3055663086122102620719264686497702155043111948238037939653973562890333039192 | None | ||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 110078217983700331842968586244622971114422588570598236491567163915283223849578 | None | ||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 81199454558722923465410547763928455086555822213662843579002130889658076325324 | None | ||
| chip_sw_pwrmgr_sleep_disabled | 94267899085811885895491062768666254341293195332256130483457059392436937197645 | None | ||
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 101388450881464089961063225040989161197003233931691792493048512315808634880595 | None | ||
| chip_sw_rv_timer_irq | 445745443364239628022401324551528883563477340307662829651010644755209204550 | None | ||
| chip_sw_rv_timer_systick_test | 36343763825494340851321830340406134389342226561355577915310849550667699039295 | None | ||
| chip_sw_sysrst_ctrl_inputs | 80296145557411914669564315769659012450332137851924855419898167190987421210613 | None | ||
| chip_sw_sysrst_ctrl_in_irq | 24927934771784741197493114833693887269772404744796251901236907383245071103262 | None | ||
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 42535293217394870579465355852704062270631607999967634753062300383167833136617 | None | ||
| chip_sw_sysrst_ctrl_reset | 66720012188999185480430898115846141997449259307974852880767405717075722816500 | None | ||
| chip_sw_sysrst_ctrl_outputs | 38507820341235565499033345137638310497117978267779637932347559073911526893561 | None | ||
| chip_sw_sysrst_ctrl_ec_rst_l | 96726968633762020002978442156699944562981524799302806482311610840450312846108 | None | ||
| chip_sw_aon_timer_irq | 113529937545255396808565117479870500493373096229289943169711713254054687146807 | None | ||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 53026483778118441581234866396985880065328331588283609380381949054065084036449 | None | ||
| chip_sw_aon_timer_wdog_bite_reset | 39984034791825673148959917289670526604940296443974811880840273134982534079143 | None | ||
| chip_sw_pwrmgr_wdog_reset | 96590391226526187342186705297209056999046505303362219635658606284240551800033 | None | ||
| chip_sw_aon_timer_wdog_lc_escalate | 101227135377861840417954070876337474906290646502357097201758769891513391186910 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 93533921832316320256372001029323855704344391000541208300935324004759819364017 | None | ||
| chip_sw_otbn_randomness | 17398605304008159145136771091609656736019905971203964626765292540525704627709 | None | ||
| chip_sw_otbn_ecdsa_op_irq | 44121873361089118165370440539100059105498810133367210679541133053454922344292 | None | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 7060238437931854458993354284164980895138939963580957179597734891950152657009 | None | ||
| chip_sw_otbn_mem_scramble | 85255242311228316101229973822498804986163654426967995369600025806622374210223 | None | ||
| chip_sw_rv_core_ibex_rnd | 56229028693916031958188239755011984454395229703014520589051579199487490106618 | None | ||
| chip_sw_rv_core_ibex_nmi_irq | 3634672680509219144020665751859753081973916293975729021135544927055044939029 | None | ||
| chip_sw_aes_enc | 27894686715730953723668361959221026970478305817226227946959275671273908300273 | None | ||
| chip_sw_aes_enc_jitter_en | 10569253512483637781900963287512480020042349983830815533755573675681943926458 | None | ||
| chip_sw_aes_idle | 50042410470759998885047604095244862443669312966470227304818684261616118893330 | None | ||
| chip_sw_aes_masking_off | 5501070155850482417938889080650268557762103077869520728841259277528558991962 | None | ||
| chip_sw_alert_test | 93287638158684433889451363049319460980173577481484713846843248541927975959011 | None | ||
| chip_sw_alert_handler_escalation | 105639983127057606745492073179314533878909372960387074906598706875000432313371 | None | ||
| chip_sw_alert_handler_ping_timeout | 65635613391634201353211522134744345357211163295649298822903499005447089715498 | None | ||
| chip_sw_alert_handler_ping_ok | 96719205173546058585887910006947827690871731204493763395954830847669041919835 | None | ||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 85171834645820745217858742189854735188372819003213901275432422862344681065026 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 15253939758079966670683005339113079508734183607671822480709615035935429004251 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 95679013280753621552664282940041072593617705428163187416877435377202451373746 | None | ||
| chip_sw_alert_handler_lpg_clkoff | 98804269991783864761819580671291065380519217701889528373228451213940889687773 | None | ||
| chip_sw_alert_handler_lpg_reset_toggle | 47076261210950521928301320586646734785368926422877136104408380931827984523260 | None | ||
| chip_sw_alert_handler_entropy | 97703610109144668187266867632635468362935996733765376304137552643722207392371 | None | ||
| chip_sw_aes_entropy | 34805898388582051022771936522842595267794564471610082369720711483508195798378 | None | ||
| chip_sw_entropy_src_kat_test | 7240403113650780393352221782073495758600992523913120279451761940466666734774 | None | ||
| chip_sw_edn_auto_mode | 54713734544713273797944803665797913630719285639450571118938164321376877370844 | None | ||
| chip_sw_edn_boot_mode | 62841490090434986419900129339143086531806872187202014541066150750489920371908 | None | ||
| chip_sw_edn_kat | 77893833007652391925624086187071540181864184390855544804187817424313669490316 | None | ||
| chip_sw_edn_sw_mode | 39286647499229760293323746670411350623975657444862420431021083898207031541044 | None | ||
| chip_sw_csrng_lc_hw_debug_en_test | 61182307996900681912397031405580841695900402010073113834209141672461029492056 | None | ||
| chip_sw_csrng_edn_concurrency | 91528648039364127574210809988873386851340891630769003798443268311607142276653 | None | ||
| chip_sw_csrng_kat_test | 51584268311618605084575433561511708068391123285704309154197766858800724320564 | None | ||
| chip_sw_csrng_fuse_en_sw_app_read_test | 101235161414713114408457359586537550509617396524758100538995681567923523616109 | None | ||
| chip_sw_entropy_src_ast_rng_req | 90556645850390178886691967004289277731994270991679688956180739756009495138942 | None | ||
| chip_sw_entropy_src_csrng | 54320779610205747962153843381598008636153933408257387317585097956823430623802 | None | ||
| chip_sw_edn_entropy_reqs | 17317817279662991248627186802330167823393903739268171728836112763457412790378 | None | ||
| chip_sw_edn_entropy_reqs_jitter | 27403606896448577140121846967684297260650000778582965062965292671287414115183 | None | ||
| chip_sw_hmac_enc | 22333257018775814393331868179814670285401558977963959891214954724555236604018 | None | ||
| chip_sw_hmac_enc_jitter_en | 4162393752692535246349092595340637199691418328988208589868890275442029269907 | None | ||
| chip_sw_hmac_enc_idle | 92527655118338051439085561723290602059944753737960337961576874627474033826453 | None | ||
| chip_sw_hmac_oneshot | 36680908573000951548960361915799973349349670446920335059063325281410859202980 | None | ||
| chip_sw_hmac_multistream | 46973953144510312748617649947879609359176452353473145566931470385139097192079 | None | ||
| chip_sw_keymgr_key_derivation | 18931188030643373686961355060836454668375151357354744707244135562279681225172 | None | ||
| chip_sw_keymgr_key_derivation_prod | 20698299572691039390395785342553083932774034684263241820584219176041461272660 | None | ||
| chip_sw_keymgr_key_derivation_jitter_en | 14082976414493990197913027880913117886835084246194311053204998503180377980026 | None | ||
| chip_sw_keymgr_sideload_kmac | 106752788655126727881506856889731955817357747896526871998286391252957866495333 | None | ||
| chip_sw_keymgr_sideload_aes | 110639651777585998837389000829672916242109695108780409695411607597832102239525 | None | ||
| chip_sw_keymgr_sideload_otbn | 19680865931583251680588643838644277941549766210800950305496868592743301246837 | None | ||
| chip_sw_kmac_mode_cshake | 84051848426034314638596865715372291749798189700565970526739814526534240990791 | None | ||
| chip_sw_kmac_mode_kmac | 108133722129654039671641007709646783762152561599616140898754955417215037658503 | None | ||
| chip_sw_kmac_mode_kmac_jitter_en | 55906762753012731528344462810730628868875517291128521884427007284053280832681 | None | ||
| chip_sw_kmac_app_rom | 82151858241790014046344661027883395741156012861950167764893434385579370814456 | None | ||
| chip_sw_kmac_idle | 62756249773933018898003230723419365061680106660824969018243786909050132052863 | None | ||
| chip_sw_rom_ctrl_integrity_check | 96150378596191092769348007034263923493293943977831252692043653463936080990887 | None | ||
| chip_sw_sram_ctrl_scrambled_access | 106642004726010365111782939629384030360746811753570591104763091086454052046398 | None | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 88294621820280091136480596115374764178895413075576639639353936726952995568007 | None | ||
| chip_sw_sram_ctrl_execution_main | 109269668405061992128506948490740566203989739910459577284785822307441087137732 | None | ||
| chip_sw_sleep_sram_ret_contents_no_scramble | 103786913496573131273851121863472590547507114273629345775471435474257333516629 | None | ||
| chip_sw_sleep_sram_ret_contents_scramble | 86791092219244842248813960915558584697966912276124993308178014755619440302146 | None | ||
| chip_sw_sensor_ctrl_alert | 75995648703729808789036369985518410498816431409955608333477525373283194971826 | None | ||
| chip_sw_sensor_ctrl_status | 46871591988898463303106284726621042183807471044108515962892574700802467195347 | None | ||
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 41018100886147256736021523178156271514430238472589422782767371726240831129874 | None | ||
| chip_sw_coremark | 82002973905067247473465206754825560666878091032379585546096104074140976032671 | None | ||
| chip_sw_pwrmgr_b2b_sleep_reset_req | 57531222573060611526215505464540718032267797818924124925097530991616086056235 | None | ||
| chip_tl_errors | 87063025887728187415527269935593570199765049790192802175754167019624990771941 | None | ||
| chip_prim_tl_access | 70065442645565295946435373158729313638717614953946584688337670979999767159898 | None | ||
| chip_plic_all_irqs_0 | 83288061798532325872389856297767281613608997982941014983412611866089208938530 | None | ||
| chip_plic_all_irqs_10 | 20299545202076742044698754808902600504779003659269266152085839392511730254071 | None | ||
| chip_plic_all_irqs_20 | 26702041805863254849877897044227536851493030041948775068532850879998352725215 | None | ||
| chip_sw_plic_sw_irq | 98837091698908670270917788903519258694054309157789194073034032417393830991826 | None | ||
| chip_sw_clkmgr_off_peri | 51883674983897234421243544482391731920896952890439761142093140607605171992941 | None | ||
| chip_sw_clkmgr_off_aes_trans | 5575378322875022457463592702381741543293945186179741221116578911560926455224 | None | ||
| chip_sw_clkmgr_off_hmac_trans | 102851261646340067103727200596500682165155704703629268508846303234073349530972 | None | ||
| chip_sw_clkmgr_off_kmac_trans | 54696282602717510890663060151204802579995759540440539704517282958186173824013 | None | ||
| chip_sw_clkmgr_off_otbn_trans | 33194649238774805157684118627184162314793292147685824205362651531680897957617 | None | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 35783478841761557699619028180938783913488855891252312581687889875336584924501 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 91912127023480870058512905110838197318873398562041703700808557831347530246830 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 54424853541371111779132565381773314673615661004965846706967782484172815228942 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 81099672094099210417840133327407687971198681749710306380707549723424272763464 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 33079991445356593660531533946416815654892767232671783777354530349130968671226 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 86095989246461682902701304599448009060774656113231391244262158102693664757823 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 3136487082117634526996067987823484558696694369039305993241747049043278473041 | None | ||
| chip_sw_clkmgr_reset_frequency | 111478915029684628330399483678796825837487284054990884911262776016821291369732 | None | ||
| chip_sw_clkmgr_jitter_frequency | 30052362768957334568740458820309667058343200789574963252431357385376183633486 | None | ||
| chip_sw_clkmgr_jitter | 90186488633184897630746595462017652618161160304255258865418500883358516590627 | None | ||
| chip_sw_clkmgr_sleep_frequency | 96029470150559955415436042071402682258243997558889710700309866514649833313803 | None | ||
| chip_jtag_csr_rw | 94361926357869528834473324016682055839781742478184568855714043348045384820659 | None | ||
| chip_jtag_mem_access | 93494687364893634565867184868346093452839745035439149473194346500040951388513 | None | ||
| chip_sw_ast_clk_outputs | 36644066796737310736765183927477065429323502705477029591141594806516646617952 | None | ||
| chip_sw_lc_ctrl_program_error | 4845545528276907333136798928026030149414594889221817643825230200195428863062 | None | ||
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 55940777229282275904529909098120771263093739766038192294221515378965446155421 | None | ||
| chip_sw_pwrmgr_lowpower_cancel | 98062449520826114631445318090932935783483339555615481324693022676073378749596 | None | ||
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 10213380524056569374634072380406333200625106778662130451529169074452486081748 | None | ||
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 115199285757841441234900088997637477922108330449423477134241203923600354541173 | None | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 104461183515700829167907624743654272808242891203578096494406818152460303560512 | None | ||
| chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 13656552666082136506522552091341607761022024526526085638169168025428452964175 | None | ||
| chip_rv_dm_ndm_reset_req | 102915534119196753264647626773686460881369711636298523955609129002892429206083 | None | ||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 20569259670061433639092396314567531632987621307396097822778307525128793989692 | None | ||
| chip_sw_rv_dm_access_after_wakeup | 113964924482248035096226929842192766168218374973994046968549166965805346966040 | None | ||
| chip_sw_rv_dm_access_after_escalation_reset | 115612566468746783072628002424644096274379525651268285582446800405220945164860 | None | ||
| chip_tap_straps_dev | 62148698270833424595301386219574179645165540469538849856832609754552660920653 | None | ||
| chip_tap_straps_testunlock0 | 106141335610948668179677439911335700411863705268514462442292150211963100262010 | None | ||
| chip_tap_straps_rma | 19741342926217439916205818617526034373257395588624060219157951799080098484576 | None | ||
| chip_tap_straps_prod | 96301749441980057862401121748406164078723530863543268589115243768808323625442 | None | ||
| chip_rv_dm_lc_disabled | 17339556716303896660090139392187158804928058621381085225504766667345923320639 | None | ||
| chip_sw_rv_core_ibex_address_translation | 103124680654551028766026584572436845261786322167961386836723040730133948634248 | None | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 36391893586967355170605526864836829530762891767076732325606664944155641666919 | None | ||
| chip_sw_rv_core_ibex_icache_invalidate | 64391854271505730609819746936437123063263898570608219598147423048906336877919 | None | ||
| chip_sw_rv_core_ibex_mcounteren_writable | 93646248231049233594670298390688767914360060038035873839112268818018320566989 | None | ||
| chip_sw_usb_ast_clk_calib | 19255278144194608679951223437091443146803169458384757318552979565641924916 | None | ||
| chip_sw_flash_crash_alert | 6441605261481710986409437985152183884301741255154603282706215891769959033104 | None | ||
| chip_sw_flash_ctrl_write_clear | 41095982436443519096252482545517033705702333568999771548920030219895967777866 | None | ||
| chip_padctrl_attributes | 4452424156778125864074847353549800649545514045321332127097413770618375131755 | None | ||
| chip_sw_clkmgr_jitter_reduced_freq | 48434512020201806819103932695758932995352788318429587447132192657505865207468 | None | ||
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 82455785689717943458513122111511287491535667227302218110443515019675564242475 | None | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 113944315341895791787072214642383498704101566198440951659496616460305874870685 | None | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 17005091010451628241911058935665077024940240705508777823503594149943199740459 | None | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 24960870124317911462973100828081888149975286514696720563045492233394409991815 | None | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 24463620545998464811375569808353028721413970746138459502601519645788835118124 | None | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 49665826242978741475260982798144250311245348687499107358594233982546667807611 | None | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 11281817797169522962083172992806875030324906364770139455430834655366275693058 | None | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 15834133690671964341743575121278092017125203504141480192247575573667132092271 | None | ||
| chip_sw_flash_init_reduced_freq | 90266271637501013052812716002396308746299960911681544941536580238370287176945 | None | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 84117548065782931765867653136862037461688573787472897631509157110400761621009 | None | ||
| chip_sw_power_idle_load | 36597815241731692861413967054657441911435497098050488917859489699957561804916 | None | ||
| chip_sw_power_sleep_load | 3633080980942892797202321874198626016528586631877708735045968348409109958209 | None | ||
| chip_sw_ast_clk_rst_inputs | 57006594246506727705861895995130231136511177185434523162798159637544866918911 | None | ||
| chip_sw_power_virus | 43272206684740294875424599774890069757152377631945678993437327810946237738015 | None | ||
| chip_sw_flash_scrambling_smoketest | 31837818723569182548563594298593700321920544078512240152528206070160442565462 | None | ||
| chip_sw_flash_ctrl_mem_protection | 58881017534466286635312484203398350143569237761919691668849153515203592218769 | None | ||
| ate_bootstrap_flash_erase | 52180689934820583910353875027536301664320731850464526347020941931651956081550 | None | ||
| ate_bootstrap_one_frame | 106552834541804202822369846086069420679087807543459176639576274836983697044599 | None | ||
| ate_bootstrap_disjoint | 74192790007861249161304347768651569273625855873929292944952208730886922342288 | None | ||
| rom_e2e_smoke | 29676983850050893059153353143659419410350648988179617641340049216452449368426 | None | ||
| rom_e2e_shutdown_exception_c | 69713758640373537206834677056496844617074045585153748097399462853446927936553 | None | ||
| rom_e2e_shutdown_output | 81992356448485689869043558916126453302347126728213850468365798079306920598416 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 54851153103417090285047975518859474233110710810567120164334067345427383443254 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 53105849582044246070400915072369664157954537511092778216462470296860102519267 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 74481538328511004263851248075088191367900246868045445620838096474663893270322 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 40448171167926559141209605458595609897301217047457519284899094762320503594218 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 115325078794403389971721943551585291448008861972016027644131990533529882293088 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 34726528287823916265444212322567723947066566195620364645918377398655239766922 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 62377901655755940852432988741360220311865140965620368672009777265386210321117 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 57161333293870818892213421011397028897618036801553433483459994610815315105697 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 14620560283183638072547567521955599216151109726676136156435264211447384921726 | None | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 12531378128577328099221415565571445919127543883390041985775734607759476628440 | None | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 30811790230010059508806871544594778461427904236913833755508509916384561161878 | None | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 97562198031622625836530137705856988646001337167652365737210133635021534305667 | None | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 31470606644787787651280602659193219301704888719734853786995882915417309387947 | None | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 46370275487925771177697552796645377102976326517261785029616274057223313598743 | None | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 27720073981388724392988256133652711015929148217569499198361404300920252365712 | None | ||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 70213385729415803513121119790579659610323289509214013009629531422566573841945 | None | ||
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 78125066293067665471586821404600126740261237987042300263175578476794997714756 | None | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 13998931435374937779697470618321718868673768662976107814399096059831991064999 | None | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 82640732744012023165198352700513952608425338963446426154660905076013108619983 | None | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 37972331506170469353243221825434665696725458369651836442768870199291146614508 | None | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 15822444010567003209076903996245556203174558928290248999691230360574636747628 | None | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 114739155585274279148872444578499841327917480269844110831781962461560614059610 | None | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 86271827169425319041100876840758647094822337355016282970690781181659387747781 | None | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 64396054566414406751490621807517497048446834627504594218822706416198375452592 | None | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 24503005374191053325263853759780346252358636375074684023507435517080245560879 | None | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 27578518829490570843495854036530787886376501153199262875403561813532825429512 | None | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 43662414814022183852891829444832130759395042663885753731259673027425918102182 | None | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 19825582048054718725008807567447953900665803624934877801430085813168181057492 | None | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 96530428674958020916533118350291644865149953487541033543325964118831913292048 | None | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 97106073879246411609868860140581659647445663151341479015546732980547698457935 | None | ||
| rom_e2e_asm_init_test_unlocked0 | 70770617040220217130836326701014732180136280254109586623088004007524306959838 | None | ||
| rom_e2e_asm_init_dev | 43221074022158699081363461730871696394563893436207169892485296273077425054294 | None | ||
| rom_e2e_asm_init_prod | 72074527604598147456501896600084896217258040144140971697387056757671903326779 | None | ||
| rom_e2e_asm_init_prod_end | 23785623510139950366422663418004136327608286067409343614530379808108452800386 | None | ||
| rom_e2e_asm_init_rma | 100164291810349385849065741920826204170301227213850324267993496125523762937059 | None | ||
| rom_e2e_jtag_debug_test_unlocked0 | 50332445086456809119392113086816887588282464015898497902493258275469406317799 | None | ||
| rom_e2e_jtag_debug_dev | 86323044396772615219289845579275552605586557201804952567169640856888402545656 | None | ||
| rom_e2e_jtag_debug_rma | 6518680171495626204792029320336356192118790942154970613542475581821306328020 | None | ||
| rom_e2e_jtag_inject_test_unlocked0 | 80401305035045414127552092831861199307424440426856756939162370469778931896734 | None | ||
| rom_e2e_jtag_inject_dev | 109051416456205453602384337768362325445488274128468604992990929634245160708743 | None | ||
| rom_e2e_jtag_inject_rma | 23320706298870276731476636991794802171862955321884648265170429254636163902784 | None | ||
| rom_e2e_static_critical | 87220083094135981322114315396374852386922300507145301395440404248662459721867 | None | ||
| rom_e2e_keymgr_init_rom_ext_meas | 20893296726377598926125349211300179644850052087536585620023797387645129505981 | None | ||
| rom_e2e_keymgr_init_rom_ext_no_meas | 69488643650809011608605063531812964530288246574835511030821061674559087322812 | None | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 81501197056096262932221521065467414142805138138491538722628040511959909450726 | None | ||
| rom_volatile_raw_unlock | 65559219404449516449568608930542144381027534879362609805863387851399410521354 | None | ||
| rom_raw_unlock | 95930212450821016618627687054085177822830549191810928093286763267193019577565 | None | ||
| rom_e2e_self_hash | 68104297779133195046810444974032415088091871968232258391863493834194552303154 | None | ||
| rom_keymgr_functest | 58990846575329563043123033896024400086621319450266753767850313801686799195458 | None | ||
| chip_sw_aes_smoketest | 40145310844282258663395317006763490784487714792525856156705982621352712051117 | None | ||
| chip_sw_aon_timer_smoketest | 44516745783685548483904124390337853814765647910541911380094039884384976746959 | None | ||
| chip_sw_clkmgr_smoketest | 101774697945567932177692546279338977590152503391804779997142930987589581473578 | None | ||
| chip_sw_csrng_smoketest | 63558963709487857352999478559358666659371426979820456004144112459020889090184 | None | ||
| chip_sw_entropy_src_smoketest | 77146425410214674933928450868291558810116899699571045309299770210684456938187 | None | ||
| chip_sw_gpio_smoketest | 35476527718627268516398972407709947162300126864195953482587933233032327280131 | None | ||
| chip_sw_hmac_smoketest | 84288806851877149850523263553994963038952835391953598429484579646283291292602 | None | ||
| chip_sw_kmac_smoketest | 107414143154277062779769196745508915393527707310835779730574012055775205418631 | None | ||
| chip_sw_otbn_smoketest | 96571342827295803231453924788416236936580581217749043141770057246365644106736 | None | ||
| chip_sw_otp_ctrl_smoketest | 55179365641231506112986680489765266724747540638529430866435626284329985015019 | None | ||
| chip_sw_pwrmgr_smoketest | 67389445751182451309464887349924648647540085083516075911726052127386102848318 | None | ||
| chip_sw_pwrmgr_usbdev_smoketest | 8510659021703209844474370100925781246121335826701697738200354823613682227615 | None | ||
| chip_sw_rv_plic_smoketest | 65982539744846493515212340788921586027203044792179589139655710713965313756142 | None | ||
| chip_sw_rv_timer_smoketest | 67277027746565051708891662127202782926154337534148609805572248117436903108861 | None | ||
| chip_sw_rstmgr_smoketest | 31546756065938754427189161029961556260328002192402720794585569161720574954557 | None | ||
| chip_sw_sram_ctrl_smoketest | 2644118428936135607674055770907849189435546368699869307202105913283323027740 | None | ||
| chip_sw_uart_smoketest | 4309302612448604577053668835446115095470459400299585545304871516803546664635 | None | ||
| xbar_smoke | 114546994161982859420461127769024420893201260771694539160746063318027494555949 | None | ||
| xbar_smoke_zero_delays | 91651478411487937464532197985415767242586281207608446862718821016903397648169 | None | ||
| xbar_smoke_large_delays | 18239955380292952538105871209742447162902268948927257546779997513941963967516 | None | ||
| xbar_smoke_slow_rsp | 81481927338244926480960921548541317592172814107955104686311433485982592803016 | None | ||
| xbar_random | 79413215823285500916151418795570617615605704249426407765001400063421699773031 | None | ||
| xbar_random_zero_delays | 96941835882644159125564006690297568784524276414461159866828107811176708249798 | None | ||
| xbar_random_large_delays | 39841378665634871361911602753442748528457087915480693812400538947488770958720 | None | ||
| xbar_random_slow_rsp | 39959247578155479046292445243943331873094291397740671602229834091943692393524 | None | ||
| xbar_access_same_device | 65346210813022387532430329176042227993600274224117792521930010431427273955530 | None | ||
| xbar_access_same_device_slow_rsp | 2363501619530847305775973097499450777298572882306498282292086532759300069475 | None | ||
| xbar_same_source | 20224796417145548385069290127231830754049042127351949143311275899528504626425 | None | ||
| xbar_error_random | 19476529176453837034953512192071056981186889504217722672799038769846449941536 | None | ||
| xbar_unmapped_addr | 10360597014748377364306103771507190347558616235085683879589046627186571508987 | None | ||
| xbar_error_and_unmapped_addr | 3399060692792330779451720423855618186602215806099772364078793638604812957803 | None | ||
| xbar_stress_all | 15571346033228791868836982361004818194350168542708238038244719075264874277926 | None | ||
| xbar_stress_all_with_rand_reset | 104814249318621526638798998037368045572423966529314771742697583721212001290344 | None | ||
| xbar_stress_all_with_error | 17971862562344736313508552355408945535310430438556169773997309859192539545488 | None | ||
| xbar_stress_all_with_reset_error | 66053782063962103875824796125289591044376998063219952833321563063067088353965 | None | ||
| chip_csr_hw_reset | 25834556605563213046586488187372704005123061379688293226855324828873384609361 | None | ||
| chip_csr_rw | 50987654202741884446547433509630334965799092542839461995393473128175436804648 | None | ||
| chip_csr_mem_rw_with_rand_reset | 51991065824099295385646535222538139438252445595070045979957437644362636416519 | None | ||
| chip_same_csr_outstanding | 114307519385207525911329729940101540346343370310527235788051587171231476938240 | None | ||
| chip_sw_example_flash | 64746000921967234827397497996569647362966446966667093860319701268882970948501 | None | ||
| chip_sw_example_rom | 77391338769676532384571672016078890351588721232722381893352203924943723115534 | None | ||
| chip_sw_example_manufacturer | 93444713803205093464912670256354971588521174700177670683611976860551024268100 | None | ||
| chip_sw_example_concurrency | 6856599321529317364586196487005321476283826632299358432934130509740086150281 | None | ||
| chip_sival_flash_info_access | 79009284202252703252799001482828344931731058285139752035284576656203634289681 | None | ||
| chip_sw_all_escalation_resets | 108096112675658592028765494865570052922504560006818164356929887926145245458409 | None | ||
| chip_sw_rstmgr_rst_cnsty_escalation | 105976680141946613397676806678362808251417994209065221645500167748643308078850 | None | ||
| chip_sw_data_integrity_escalation | 31228012016332344792584267465501022434831388667160313287287911181785011257472 | None | ||
| chip_sw_sleep_pin_mio_dio_val | 97630981418711796582063407754787500755569246666184790433228984901603345085819 | None | ||
| chip_sw_sleep_pin_wake | 114104132355802559778449615303364417152909783584410347562309063267620840998178 | None | ||
| chip_sw_sleep_pin_retention | 39180207282784399904084147356213858436831614233843094642091862950073790346795 | None | ||
| chip_sw_uart_tx_rx | 89444316295951844542339775197800449949335962594336931478359834474939298634522 | None | ||
| chip_sw_uart_tx_rx_idx1 | 88597002614694804966061572132942255589248108094009607559957253719619182808850 | None | ||
| chip_sw_uart_tx_rx_idx2 | 107183841919716706212076626394495014208999020267322813452476021344525107475086 | None | ||
| chip_sw_uart_tx_rx_idx3 | 26171663761029107250314428768953538062072905958105331822909003624301094038432 | None | ||
| chip_sw_uart_tx_rx_bootstrap | 109802093717327015045266333245026938277310319526081308665207115317158330897010 | None | ||
| chip_sw_inject_scramble_seed | 19922113005287053846460338767743075495344133701262190398725733494412706112392 | None | ||
| chip_sw_exit_test_unlocked_bootstrap | 5710661069889705116439481748387126537454190133866606535027551057346289597965 | None | ||
| chip_sw_uart_rand_baudrate | 34441995610468495535397467418744172862289227085528434209770088993386089533992 | None | ||
| chip_sw_uart_tx_rx_alt_clk_freq | 20922533372310030286642477292348545899947736644204590672264154679394780458093 | None | ||
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 53382296713961722610694189813848803495873263888294675526595141917682975453059 | None | ||
| chip_sw_i2c_host_tx_rx | 70770751591123595646062425065339262468740371868148983789269359229126474007593 | None | ||
| chip_sw_i2c_host_tx_rx_idx1 | 78690976526751001523380983053981695581847245413072726139305833224562949026732 | None | ||
| chip_sw_i2c_host_tx_rx_idx2 | 90395693999105143543843148818961644948437586056017098435430015799961592383196 | None | ||
| chip_sw_i2c_device_tx_rx | 28977468716030012920513562879786664003518713068206613153015216043524195608990 | None | ||
| chip_sw_spi_device_tpm | 102249631459880053165113623749974080214131102745430629659605687473628672566533 | None | ||
| chip_sw_spi_host_tx_rx | 47085085557267502803498152060715175891416270662917370940906849303230698018627 | None | ||
| chip_sw_spi_device_pinmux_sleep_retention | 5663116150346812946723205741464952136092585168274135212450658409678788210244 | None | ||
| chip_sw_spi_device_pass_through | 70992187171466550985751356953851962222257454856337321778139390099441353029310 | None | ||
| chip_sw_spi_device_pass_through_collision | 83260553726422747294330209116670227220499274314054793002329129383264155719445 | None | ||
| chip_sw_gpio | 90130367070807335428029951813123139410856277792891571816294766408285918768544 | None | ||
| chip_sw_flash_ctrl_ops | 59534904567468092269708890647746639377510378903693900394255293679926186368388 | None | ||
| chip_sw_flash_ctrl_ops_jitter_en | 86834673086524642432847728179964709186759540312729813874834642564689128780542 | None | ||
| chip_sw_flash_ctrl_lc_rw_en | 100913681674122378851513556171514606431817434685302946798267982524809180125492 | None | ||
| chip_sw_flash_ctrl_access | 42499737507415226582714276816163713344745160190386354716635174822941287830225 | None | ||
| chip_sw_flash_ctrl_access_jitter_en | 33153207130137529896863754456987557573604464268383768801656196934115711556301 | None | ||
| chip_sw_flash_ctrl_idle_low_power | 109630507283886386888205903862532769253244407870061647814738342135743042934453 | None | ||
| chip_sw_flash_init | 49742039775886858326151349575044570489420436889885435600385164891676399266430 | None | ||
| chip_sw_flash_rma_unlocked | 70452313744035077224743313578204251064176330909863950620287102569093764310247 | None | ||
| chip_sw_flash_ctrl_clock_freqs | 40747659839501418587788767646514324243070125866580455640439608703758758695415 | None | ||
| chip_sw_kmac_entropy | 86359318504489723669630581923104173079372864494202635447356263486289792389221 | None | ||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 16238504123552551365932309652553982382315470508279846301427687889193027182813 | None | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 110052216516087281967040069314561147051091605625415635214438903585819493318308 | None | ||
| chip_sw_otp_ctrl_lc_signals_dev | 66906943371889851403348513516298941820779613977155681879720208282219106480139 | None | ||
| chip_sw_otp_ctrl_lc_signals_prod | 107311420422487107376611325774901193080715752511936660378844631123652298010185 | None | ||
| chip_sw_otp_ctrl_lc_signals_rma | 39980692984519946243249791081882226394837377956297334309155593113931403589939 | None | ||
| chip_sw_otp_ctrl_descrambling | 12696837814345796338571792712663846660772535368929131881372979211527793913023 | None | ||
| chip_sw_lc_ctrl_transition | 67782983573204042522337699524235163691757047017761573220347740786856877771156 | None | ||
| chip_sw_lc_ctrl_rand_to_scrap | 98340013170064312434200107033273971871003143754277492819836643035683442758961 | None | ||
| chip_sw_lc_walkthrough_dev | 109108068738099326835818173709951135403092470671028547813339400844878994170538 | None | ||
| chip_sw_lc_walkthrough_prod | 102691098961666052009646681646552747776715833214119841754937348460422840622493 | None | ||
| chip_sw_lc_walkthrough_prodend | 34022958585987022439360195555126429179017142276804778140056947458723403300156 | None | ||
| chip_sw_lc_ctrl_volatile_raw_unlock | 111133744157691125296510484245336500891051095116038094992793358626188223812056 | None | ||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 7090638008932935998093297027154235099093441831475007979401894267857182353979 | None | ||
| chip_sw_lc_walkthrough_rma | 108794015857399630352897319340927030790002566333515303408517002649314545257314 | None | ||
| chip_sw_lc_walkthrough_testunlocks | 22487705727221275357883333148071544280327318083495854529789250785370845472919 | None | ||
| chip_sw_rstmgr_sw_req | 109221103226590805097553092523116512326249529355225988984059131818413293280863 | None | ||
| chip_sw_rstmgr_sw_rst | 45925280611026788632740629823384345685185780875865245257505331838015669135587 | None | ||
| chip_sw_rstmgr_alert_info | 100353629067033830118114795656575463975356291901786004246917929449161670928197 | None | ||
| chip_sw_rstmgr_cpu_info | 35321157150331940521024508371841897904317881160846267169255226333795661133524 | None | ||
| chip_sw_pwrmgr_full_aon_reset | 34810128216432059210456271392654907313443079779451757023380011180638573411634 | None | ||
| chip_sw_pwrmgr_main_power_glitch_reset | 104047916704124158079770930527925783873899248689913076994119011819507494332183 | None | ||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 71899996001953606040449556320393973094257261064843580082360797904526620571249 | None | ||
| chip_sw_pwrmgr_all_reset_reqs | 59811398356859058907059973002095394258199185740130750249639692348361489454357 | None | ||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 55612712329494893715822354927311551520092251323945045467366217836621552851740 | None | ||
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 96506630412085102788131418366472206537959074521679405058921183273139783130375 | None | ||
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 27461604218443183599285019188822344781683293654353048223526054508956976165717 | None | ||
| chip_sw_pwrmgr_deep_sleep_por_reset | 33240366486182494020187728978595662787510438953924637241948930829385915219911 | None | ||
| chip_sw_pwrmgr_normal_sleep_por_reset | 92157217087034683363022583049598127254831937519219827157815002729596893946256 | None | ||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 109408884800641603474653797168839417001845997259036889786632137300878755011990 | None | ||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 98092745164894877708547625926020026097658115979241998441502993879750194301281 | None | ||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 100726067392728194480920109595639117850663899029010871753070853018745369650839 | None | ||
| chip_sw_pwrmgr_sleep_disabled | 13899347235206677003066847001800487024793798037833819893323116981649481804336 | None | ||
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 50433998045213158625745353507533530874146032714374682551010407121675389328865 | None | ||
| chip_sw_rv_timer_irq | 105869715377075281312181081859681567375146047166185270987114264535980648347151 | None | ||
| chip_sw_rv_timer_systick_test | 87359494505621208182498487680573341706833653117287539574984326172330369188742 | None | ||
| chip_sw_sysrst_ctrl_inputs | 77836895113499367172203831458650404703119175512326894638404749816133947440153 | None | ||
| chip_sw_sysrst_ctrl_in_irq | 75253479697879629204004475346747633765730289222401769714636974571826001318909 | None | ||
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 64141783965379208779086375257664364022855844905965866584379107147513601711406 | None | ||
| chip_sw_sysrst_ctrl_reset | 2659414646925323520286024971896031058895738690459033144002357116135245166010 | None | ||
| chip_sw_sysrst_ctrl_outputs | 106320726854199657922953828850178155341706280515319924811662350934802025746573 | None | ||
| chip_sw_sysrst_ctrl_ec_rst_l | 30599886279878561946198100132148235354266474738055145339151862695352961942864 | None | ||
| chip_sw_aon_timer_irq | 107153111097339564039519319197639035083653217265724986736339117182990723359215 | None | ||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 49479480755317253755704076930923997270504422188642439833822215015839716963185 | None | ||
| chip_sw_aon_timer_wdog_bite_reset | 45277998149113795100973864126427118741337383550058548405068689732431406908263 | None | ||
| chip_sw_pwrmgr_wdog_reset | 28639904480123024744568515326006548981034473352111809784770440888464914482177 | None | ||
| chip_sw_aon_timer_wdog_lc_escalate | 54409663190508827919045970565753750064619954081678457256581214790292120691005 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 49388846061349250537212549650559236682216165171057466048370226947173592578732 | None | ||
| chip_sw_otbn_randomness | 33115549817952492752554132227107861367801042556802011427150305749139129356127 | None | ||
| chip_sw_otbn_ecdsa_op_irq | 103983928606682239015340087253176229080189563872516293391751567734308012378 | None | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 51784895898217826275344560359439994123231314051885521789228369457514577107659 | None | ||
| chip_sw_otbn_mem_scramble | 103570655094153462774161377305920518459491296551278276798144303463655477694505 | None | ||
| chip_sw_rv_core_ibex_rnd | 11616313740041894250560605021449743979874200701877374631796879900284388582792 | None | ||
| chip_sw_rv_core_ibex_nmi_irq | 105152593439086407275384869733840557438908186704321482209826566399044102292177 | None | ||
| chip_sw_aes_enc | 29533355278280456959493969704383202424054211379504762690282966752055815221984 | None | ||
| chip_sw_aes_enc_jitter_en | 18143918747978158566128118202891043047672019915059579361513332868048825458194 | None | ||
| chip_sw_aes_idle | 50110434017460540724339156273367268758534231309534746392410527097840927038049 | None | ||
| chip_sw_aes_masking_off | 65690201468584061537931563369544198396533662845211261437593352805169233788857 | None | ||
| chip_sw_alert_test | 13297917861949419940906773981273234245619547562253218547597666723308209965869 | None | ||
| chip_sw_alert_handler_escalation | 43483596960136104937159399972610824674252278017063499616203819355070225527499 | None | ||
| chip_sw_alert_handler_ping_timeout | 50285040872576229324426821875518687983145468159564183417469364577942834648399 | None | ||
| chip_sw_alert_handler_ping_ok | 46017697866948900470058700505020115339736172384782360158703349030752447734491 | None | ||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 29483050617088704955095135073639810468187538289013220929384738722180572818245 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 83108017925780299290198420779233583510593781072416292789647694708625957510952 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 69814314916806625853952356333375316358352555682611871349814300221844099728705 | None | ||
| chip_sw_alert_handler_lpg_clkoff | 19726375369329621501814440311394968955541920253174304199458402376246141170831 | None | ||
| chip_sw_alert_handler_lpg_reset_toggle | 95213595147532875863859927782258703293252341385117654872894786655614745312331 | None | ||
| chip_sw_alert_handler_entropy | 18051649608159405794262716542751658285000777448335344045394759144227224707133 | None | ||
| chip_sw_aes_entropy | 50113798173470817906609551324848454314914850094786714351218212593691880264945 | None | ||
| chip_sw_entropy_src_kat_test | 44049313144513886754835147240715419360981700567815615381224921169524067065994 | None | ||
| chip_sw_edn_auto_mode | 102533884147757851177258417029606218722111533071960319481481068568667518362827 | None | ||
| chip_sw_edn_boot_mode | 83309402886677012207808945524827826268766019436043817647341924904411179895267 | None | ||
| chip_sw_edn_kat | 112235982962187690714912149916064725313865458576867066232947146325901953069640 | None | ||
| chip_sw_edn_sw_mode | 90472288130985387423540675381828070546763875382415543313390341718784006747645 | None | ||
| chip_sw_csrng_lc_hw_debug_en_test | 6218827928347116050557073359977467495445487633074722653535028562680996682953 | None | ||
| chip_sw_csrng_edn_concurrency | 7728862526277766471543841753664040574004639970929587621488881416804465948170 | None | ||
| chip_sw_csrng_kat_test | 66211400292169246512119209326075631330602352086749487659816097668348471036799 | None | ||
| chip_sw_csrng_fuse_en_sw_app_read_test | 51856440378033029620643353796649909997366455857659161778941439793490588247044 | None | ||
| chip_sw_entropy_src_ast_rng_req | 25762989572653316760966291160794700774996133091827037673781204346709371943371 | None | ||
| chip_sw_entropy_src_csrng | 73883853942895375016705006639654970991471944535527957671946700363151526161982 | None | ||
| chip_sw_edn_entropy_reqs | 29243082404656577523076390417645526163347209938816306262482464212920688741753 | None | ||
| chip_sw_edn_entropy_reqs_jitter | 91330066529151988327802949724232278458000821055495347946955085301656061608984 | None | ||
| chip_sw_hmac_enc | 61834347183215300298475605513020067818326016840364193358992382947448070084910 | None | ||
| chip_sw_hmac_enc_jitter_en | 63603081378331735378359387819014420762962830804726660027157469723017177768641 | None | ||
| chip_sw_hmac_enc_idle | 94465991498107590904898293219398483560747826696700930023417376983722632096935 | None | ||
| chip_sw_hmac_oneshot | 32405035581866779784951746405445821793110868823715121176783062167399053319515 | None | ||
| chip_sw_hmac_multistream | 97390751921703756443459140921597190214586435698587919218073272896923341898786 | None | ||
| chip_sw_keymgr_key_derivation | 65573883196956385207096683830661358620380502973525038074881464725862086610011 | None | ||
| chip_sw_keymgr_key_derivation_prod | 103810196623586326116547871625518338114309916433247075203521884203676492199536 | None | ||
| chip_sw_keymgr_key_derivation_jitter_en | 58679430692950578153234427181828851680368885979837866879229537243689220726636 | None | ||
| chip_sw_keymgr_sideload_kmac | 64861453826219412855180998526378914124595006043768357157975004002483317493687 | None | ||
| chip_sw_keymgr_sideload_aes | 3072441610876367390756747179083674434489869677866712462870040658086326677205 | None | ||
| chip_sw_keymgr_sideload_otbn | 69937968933635634550763213739590441272841124152342910091421230119947731490679 | None | ||
| chip_sw_kmac_mode_cshake | 105940490571663945439086985566601124151126444213777718751763988843196363501107 | None | ||
| chip_sw_kmac_mode_kmac | 114446462751649187449726466395772756095019528479443409254841649432301938137799 | None | ||
| chip_sw_kmac_mode_kmac_jitter_en | 50134504633656380945357425022850370006941356149750924342719179481194687584718 | None | ||
| chip_sw_kmac_app_rom | 12371667121638810209807764607403306805944633715298085290587210472978505835560 | None | ||
| chip_sw_kmac_idle | 62662284750265526028860544921230210346182957836155174951799760389495042250448 | None | ||
| chip_sw_rom_ctrl_integrity_check | 48119558306294874790212233617999928370592201646295028606471733785522144031218 | None | ||
| chip_sw_sram_ctrl_scrambled_access | 102003674820574815338352027153407768154891858082113438241075558186817156480804 | None | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 21707380668931842654421254645577517341591507612730261794624050547581810674616 | None | ||
| chip_sw_sram_ctrl_execution_main | 53190735699009312607003258045372933076381871085383976694386560483178241337657 | None | ||
| chip_sw_sleep_sram_ret_contents_no_scramble | 60660146631510621012855991213335331021257052076216369032269722157323524496826 | None | ||
| chip_sw_sleep_sram_ret_contents_scramble | 60820471558077409504648780252028913609035582021892977169514069791981809694312 | None | ||
| chip_sw_sensor_ctrl_alert | 76636328542583149532675815090496063704268717801744801792813719000676615388291 | None | ||
| chip_sw_sensor_ctrl_status | 103125946349448752846087830776346089704942219905707116437824420564475906171079 | None | ||
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 106621554431453282186035262478326611081640028890442130283116640685063392850061 | None | ||
| chip_sw_pwrmgr_b2b_sleep_reset_req | 12878833185001526802084829205736157488802945723936320496967426115987181358175 | None | ||
| chip_tl_errors | 111410815111443061565728954602446494452438269147843556150431361846893124624134 | None | ||
| chip_prim_tl_access | 97370119913427841024958025909478783371296953511947233447435397565079906297773 | None | ||
| chip_plic_all_irqs_0 | 101703106570342813899063906905024379809404461030914153689579243176305113821126 | None | ||
| chip_plic_all_irqs_10 | 31450559985691455491345339936506556683401518222830615662861237404244047371520 | None | ||
| chip_plic_all_irqs_20 | 5458967571875352772827681355054448254062081001129295207306428534037323928304 | None | ||
| chip_sw_plic_sw_irq | 100948717975242533359785543593520764392299081324370489658343253574042105307954 | None | ||
| chip_sw_clkmgr_off_peri | 108816003332459049773986348017825810138260587921086673188729769982717864092332 | None | ||
| chip_sw_clkmgr_off_aes_trans | 24508662628801397043323831106834190539369316630895946434350451131860991082787 | None | ||
| chip_sw_clkmgr_off_hmac_trans | 50384813621530095271219330453033246349547532959722248817927992948781144088131 | None | ||
| chip_sw_clkmgr_off_kmac_trans | 5465971114722207888263382514755799552619343290127873628512975930216858121962 | None | ||
| chip_sw_clkmgr_off_otbn_trans | 58586610095075875636190588800954091181547320873011358430527819802775756349844 | None | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 69374713910538352947955244422932427153919368486531706121617070104369195087430 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 82863745050802089913716409847544038900171797408750873965493996377087199976787 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 44094184527798159312381890370757896019133967229827004850445263633751934375983 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 112109230953169236021151493659061463068307982724293745156375132312717208660602 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 31465933811490303534173423099989675386426970845885621800781610453386484969753 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 58526894210182100317248013348328989092186953820580428597151442671682845438068 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 92256016910364461637558472848146177099599304004416381109116157403963889667781 | None | ||
| chip_sw_clkmgr_reset_frequency | 59321241009460387823280928164426910643863396369104839711329478422820299077758 | None | ||
| chip_sw_clkmgr_jitter_frequency | 2634806584364654060387174060901796150343075176252606406262712283440164926338 | None | ||
| chip_sw_clkmgr_jitter | 3619092723432239802554761288749366501381404770959411894933578371038054022568 | None | ||
| chip_sw_clkmgr_sleep_frequency | 74033069057716422187128769431846404584010790768953990356860272708420688047488 | None | ||
| chip_jtag_csr_rw | 3423309901231418094396714842415594844234535879726988589441402915408166693870 | None | ||
| chip_jtag_mem_access | 71325469932685542453426948028771581195341839004947557028083574196477631223198 | None | ||
| chip_sw_ast_clk_outputs | 75677438291058235744430251629720796594776036655778102235274453396744138833736 | None | ||
| chip_sw_lc_ctrl_program_error | 104600892686597969169864760973372442014770056923361764316273763855801408627286 | None | ||
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 103784596312172394132594569366069832809112937801742015196766890021651607710458 | None | ||
| chip_sw_pwrmgr_lowpower_cancel | 104004774457174393228831680668622961010288076284155359955187012311765240197526 | None | ||
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 41418200239028646612647596983798269977082254481774869695053557276423696489544 | None | ||
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 6411039945118317266961902609668153510779000957462672098430106797467248756254 | None | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 107176489614249038726961435122339673243200809653988483059127852604602617459363 | None | ||
| chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 33637705820487791835328109297173451020001168353853674530684606435232029029013 | None | ||
| chip_rv_dm_ndm_reset_req | 47331995762671044880468488408283153494005094519990898258278805509823669096387 | None | ||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 100708620808444481880950287645738156096171168883396243381079268097887196625614 | None | ||
| chip_sw_rv_dm_access_after_wakeup | 15862304685740991704655117157016419305001684933362657864039983682622004222326 | None | ||
| chip_sw_rv_dm_access_after_escalation_reset | 77269301747474184157085961252139943275046916246138643149775765317289535626008 | None | ||
| chip_tap_straps_dev | 25584480266207775985089279860224023942808559972814325618010883400801346224602 | None | ||
| chip_tap_straps_testunlock0 | 72946186724100209431116852544131649561979357847705965375274670439394838760914 | None | ||
| chip_tap_straps_rma | 105975930439932382457885494935112411635136748383443009554281228050787595688298 | None | ||
| chip_tap_straps_prod | 1061005761405182886997239202152542055828792951810127668579099178652349377019 | None | ||
| chip_rv_dm_lc_disabled | 67916131378962755895543016316732562955606739076557784823215480832881615027571 | None | ||
| chip_sw_rv_core_ibex_address_translation | 99731914991132279684075635766526172238295683025133007759630264807946642983940 | None | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 27999981183833326646472981914241859500923744955370214706668289241506640222324 | None | ||
| chip_sw_rv_core_ibex_icache_invalidate | 52739485306678376354836783204997107897261283132873392331755755203692515344509 | None | ||
| chip_sw_rv_core_ibex_mcounteren_writable | 304836717349915258907952649960899583112531201016442052313090820134019160700 | None | ||
| chip_sw_flash_crash_alert | 56061956611457540048990159711291430521935226005594838033742884986050413110240 | None | ||
| chip_sw_flash_ctrl_write_clear | 83173801381159402060680583223530997167897526530037389784746311151425400784499 | None | ||
| chip_padctrl_attributes | 66829091328384721619024332895085410828854929390257596112390242891973320799343 | None | ||
| chip_sw_clkmgr_jitter_reduced_freq | 28142922327396619020737179580523800539918756247354626679810441322742610834438 | None | ||
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 99754186948149118824216214662994470664580336460018120969333117140801347750739 | None | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 108266168752684950620936975673643907651975663287469565238785708112049304382633 | None | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 3765473376588586578143040711353932071906821968372874500029954032831460200060 | None | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 26509460159791677402126820827632252844778889159081814065353749446804616402996 | None | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 22247656163602627124060941643864840962882688568560002389022906876697988796507 | None | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 31082556532657067973301268296817440637419181017020074663988783767629080466312 | None | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 57371229219370056280013702085466601297640437399285893514232104511449776768969 | None | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 67357651429597886608917900919611491338108621599625325308552786324372717621088 | None | ||
| chip_sw_flash_init_reduced_freq | 49329321227488409119201314409302227531574362701285347840167414749975360816446 | None | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 6883827541623741083967941109709404579250786723088580001922347550428751416610 | None | ||
| chip_sw_power_idle_load | 48982362780937427693032394820846863674970389378257082524307381690280633548313 | None | ||
| chip_sw_power_sleep_load | 54215569592056993445912481020990513515400069479642605207257461085586141362539 | None | ||
| chip_sw_ast_clk_rst_inputs | 113182108106592002801169457785918000744458803400061776989057373094962307239083 | None | ||
| chip_sw_power_virus | 115053448721705555513920276455468906500794034129524720585003399122878749125486 | None | ||
| chip_sw_flash_scrambling_smoketest | 26574444843635115492632239271322944352472791222402166808110498950608225290837 | None | ||
| chip_sw_flash_ctrl_mem_protection | 78671418880279112499218452136619586115164833146208501326254268222581568508761 | None | ||
| ate_bootstrap_flash_erase | 7055179175654749471593098474471221684957452151656363225426175721432815934942 | None | ||
| ate_bootstrap_one_frame | 109788949611552159063818117111880265686547815269294159480599307008595789259005 | None | ||
| ate_bootstrap_disjoint | 1450335192584985793997576424959115942754520804420095299788951382498226372117 | None | ||
| rom_e2e_smoke | 10596752293659803418008506028093746041461469468422208934559271612572624053497 | None | ||
| rom_e2e_shutdown_exception_c | 7465406143496088307347526662218444553344393643352770706313333080700889088242 | None | ||
| rom_e2e_shutdown_output | 30914227648847060332532022147217003566533379123359855927910434794291488517662 | None | ||
| rom_e2e_asm_init_test_unlocked0 | 21737483807587676366696524495423348595884421213028875566053112950674252226059 | None | ||
| rom_e2e_asm_init_dev | 4816356007358399237255575110172317823827545265873415930319509370592483797765 | None | ||
| rom_e2e_asm_init_prod | 626877649535097359236817463199617696586252235040143541645381773216106083028 | None | ||
| rom_e2e_asm_init_prod_end | 66290444649989250576663386928112531539163351034836633551928584140879052342477 | None | ||
| rom_e2e_asm_init_rma | 25816322316990597255265973003111206190245509313735492436663162097259175732956 | None | ||
| rom_e2e_static_critical | 57799575109926355339620174163524017515066304878255816423216146354227639923400 | None | ||
| rom_e2e_keymgr_init_rom_ext_meas | 23730285288208403163861563675771757873599000307473062725038011263501076153149 | None | ||
| rom_e2e_keymgr_init_rom_ext_no_meas | 25213842188465743936015631557450022076614969684112852612757170442401963166377 | None | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 104138017487672230764375143041028022211287717461487182947339984321220098742695 | None | ||
| rom_volatile_raw_unlock | 101783892515093759265705284816189532993673810326195910921708695988701027820137 | None | ||
| rom_raw_unlock | 43365241844631704943556854027984209418601746840693399895148691813512595449618 | None | ||
| rom_e2e_self_hash | 21455302295780165844522205253095099946748893981438641297204899718712831489003 | None | ||
| rom_keymgr_functest | 29813385099008511530665982228867791543876867315618437251295347227091688605086 | None | ||
| chip_sw_aes_smoketest | 110790888055808220688514792646451491123658104501385079671574098967671429595498 | None | ||
| chip_sw_aon_timer_smoketest | 32281955400079921422570505038790468634140009774299688267366865985978981288378 | None | ||
| chip_sw_clkmgr_smoketest | 46190997287473407675354690947646216547437664769402661702394667104221368295757 | None | ||
| chip_sw_csrng_smoketest | 62697499449621947842784163104349725977114338817551529662391557407582832408553 | None | ||
| chip_sw_entropy_src_smoketest | 92426071265892698966793500133996657226270252614042242329470280518810164652771 | None | ||
| chip_sw_gpio_smoketest | 16356710767123847382276894056875627853793600297584322840066067417765313449656 | None | ||
| chip_sw_hmac_smoketest | 51743833139558997226246581814917256199794393852510527778957769060980894531194 | None | ||
| chip_sw_kmac_smoketest | 16339190176600264434203759435281117937815289223843219063739904160515137029855 | None | ||
| chip_sw_otbn_smoketest | 66781237765721503623258563082402945718617433489555255914014923148481966222640 | None | ||
| chip_sw_otp_ctrl_smoketest | 112394349110348396061495187130482286220856168791057508435136479033864583645387 | None | ||
| chip_sw_pwrmgr_smoketest | 25625559206497303911582043075733730376624556247092741874455699707128521420594 | None | ||
| chip_sw_pwrmgr_usbdev_smoketest | 98444988362370055513999505917100764483441252647962581441719641460685925905788 | None | ||
| chip_sw_rv_plic_smoketest | 95191612521218726538987101361645590482338793571446531077436668746989748934400 | None | ||
| chip_sw_rv_timer_smoketest | 108529323864414373377616375512568355300024768688349007810250277806187962628824 | None | ||
| chip_sw_rstmgr_smoketest | 54175171843812652841201759331196092462333314228112833847418896413957041188984 | None | ||
| chip_sw_sram_ctrl_smoketest | 7411225314008940656939077044164933167807800957700711265887877468382847989264 | None | ||
| chip_sw_uart_smoketest | 69913556889923752335174522606338042104962812334821495999624654188663381062039 | None | ||
| xbar_smoke | 74894844014086488138580684453119157686832963014947384906775270875183645120490 | None | ||
| xbar_smoke_zero_delays | 70836089387667242335045097844941698024970056441844091100837992954254149053974 | None | ||
| xbar_smoke_large_delays | 53134840919115271734913615128255336753049570965703077962832278569929872042101 | None | ||
| xbar_smoke_slow_rsp | 42451474841478347981402206769348242053446299908283980034773031382116406750427 | None | ||
| xbar_random | 73677122485517022933831161955102109875157095515133525078699030303934697618075 | None | ||
| xbar_random_zero_delays | 65168229805270838780429082002671389947503457014920632112293507069150833573550 | None | ||
| xbar_random_large_delays | 41047813973754058784911202192580129990597423610115783609934196705932143003529 | None | ||
| xbar_random_slow_rsp | 58327751681501150880242786405788755677354004040386763765562582327753900022312 | None | ||
| xbar_access_same_device | 11267546805110212549165389192513186666914127280626187235606193028267361351200 | None | ||
| xbar_access_same_device_slow_rsp | 108033363887720045366386227257536043425001260738021429510925817326423122141888 | None | ||
| xbar_same_source | 101107388043052921302352255102974539446707998616421894013782590061638370827433 | None | ||
| xbar_error_random | 28751354523172485036695113842957438546740115352165340416141119471865834721485 | None | ||
| xbar_unmapped_addr | 92638914577593380453992112796186231984530286842700348378131100420481379853808 | None | ||
| xbar_error_and_unmapped_addr | 33100934491662351367318252512630797585403769446664112374925768991488958007422 | None | ||
| xbar_stress_all | 63578632681576313364751495389177760791159013917370754223455539102283751994314 | None | ||
| xbar_stress_all_with_rand_reset | 18241163651025902916758138775864740214319745823705357915532227244970656521928 | None | ||
| xbar_stress_all_with_error | 60747331775533682785801819571584758009611218606703338411909724152219364133926 | None | ||
| xbar_stress_all_with_reset_error | 51871596929643210302742132050524064555588802894515439435445800490215075210817 | None | ||
| chip_csr_rw | 80465065741742708513079184079389681006862660984104759465050137790366432732447 | None | ||
| chip_csr_mem_rw_with_rand_reset | 93807344197462183636426546123733394304725947959671241176333739484216134332463 | None | ||
| chip_same_csr_outstanding | 50708547666089715866308978715719383871647916681354874846817942021453472205293 | None | ||
| chip_sw_example_flash | 39451050927886547193613754432005302291831274920599639497026333732808602199930 | None | ||
| chip_sw_example_rom | 82222319329810685166161937295668484278435979059143884066757612184934626614008 | None | ||
| chip_sw_example_manufacturer | 82084042926617170949420248413581456710955487791487304641192731357424377034306 | None | ||
| chip_sw_example_concurrency | 79894342064479304617994580661686638671835191718373097228904022815512982167512 | None | ||
| chip_sival_flash_info_access | 53939815363925413313372751928276832548652039416370607826680466441767542624116 | None | ||
| chip_sw_all_escalation_resets | 102882031520374567739720753852639636286565460047257666846801643298715436116621 | None | ||
| chip_sw_rstmgr_rst_cnsty_escalation | 105511170485828856922314128709054307369803730345681902203553539422762395643329 | None | ||
| chip_sw_data_integrity_escalation | 66492061841315829006774634191541086395002674773901552446448903679783290139259 | None | ||
| chip_sw_sleep_pin_mio_dio_val | 75937190283956043823163794323242409388477545254049539568767948996087878573202 | None | ||
| chip_sw_sleep_pin_wake | 92313013106806661789263596544449980547808486329909202572846273705662309272835 | None | ||
| chip_sw_sleep_pin_retention | 31419047144694840454845201049102553364723527795040928795811038897772889934597 | None | ||
| chip_sw_uart_tx_rx | 2196313385952809699395739674532799578804266158293172397352184227210933693836 | None | ||
| chip_sw_uart_tx_rx_idx1 | 55757579697107592373168700328298629873129292800848740169986875058210404184608 | None | ||
| chip_sw_uart_tx_rx_idx2 | 23341857178284917641762277753245301955608284917000398483193366997751443423520 | None | ||
| chip_sw_uart_tx_rx_idx3 | 28775371102572094859530898754206779503649522262342055656229739126073005972715 | None | ||
| chip_sw_uart_tx_rx_bootstrap | 2825275434074183186771351736643231869722119279477520332632502868808616956304 | None | ||
| chip_sw_inject_scramble_seed | 52061171284578087319860538444057003440102351190615595894200650739750453159383 | None | ||
| chip_sw_exit_test_unlocked_bootstrap | 109372826159933915637511864444082606949759956372415851976250095413622107879355 | None | ||
| chip_sw_uart_rand_baudrate | 69302475339353891633257801085704296345202354877925341549345158456965241712593 | None | ||
| chip_sw_uart_tx_rx_alt_clk_freq | 39246832893447348705963969429992827437875754455793269266108884600475150206508 | None | ||
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 103197090698168839682047735435752113449767118992591540013202518149716550082338 | None | ||
| chip_sw_i2c_host_tx_rx | 109882768580990051131089300858114737425588423596405610748760383181117429203192 | None | ||
| chip_sw_i2c_host_tx_rx_idx1 | 100286450547129133758018382680351982993087953500443734352328448162510061069392 | None | ||
| chip_sw_i2c_host_tx_rx_idx2 | 110217459359982485836314321008342606493939180595712794178390402547257084533090 | None | ||
| chip_sw_i2c_device_tx_rx | 21612404425860128671900539105083158061354776683875107482775429585239032358494 | None | ||
| chip_sw_spi_device_tpm | 12525956173070246960501462691908843081910511978076436198742976563199141548148 | None | ||
| chip_sw_spi_host_tx_rx | 44744046984431209174148970404402752741596715999462857291601233361287963804014 | None | ||
| chip_sw_spi_device_pinmux_sleep_retention | 38769587552051729915854897089064757666822755370669025657873106254073421298551 | None | ||
| chip_sw_spi_device_pass_through | 50598490924136689265542845279994931879142607497089151806699069410598685125234 | None | ||
| chip_sw_spi_device_pass_through_collision | 82020092538852692716173751528186735663569709272088746492683125946512950956115 | None | ||
| chip_sw_gpio | 97472127176960707186157556602978956300514894928098732080310435943826551490816 | None | ||
| chip_sw_flash_ctrl_ops | 4166088984283047630220600140790164058396972045934596721612575728662381037435 | None | ||
| chip_sw_flash_ctrl_ops_jitter_en | 111883268452272975768380338362440191319651713944884853537031072875518246777184 | None | ||
| chip_sw_flash_ctrl_lc_rw_en | 34014878118877355324606263487177086205027994660323484179049685535284187467508 | None | ||
| chip_sw_flash_ctrl_access | 93279352396672154809771505883505985020253164658458232134858598420689564406060 | None | ||
| chip_sw_flash_ctrl_access_jitter_en | 15943226237825070489132554659248019214253780978494892702698586548092529269351 | None | ||
| chip_sw_flash_ctrl_idle_low_power | 56331489111735663669144242974584754547464812175208068002046901402213845898837 | None | ||
| chip_sw_flash_init | 83814899716057759224311037900958655826446046547380271371597448790072315448928 | None | ||
| chip_sw_flash_rma_unlocked | 25502985392980836761539947842903395069735847182706260608095751978969307656023 | None | ||
| chip_sw_flash_ctrl_clock_freqs | 19504339377006765919855570865258618294919473869436134955875752692561778829895 | None | ||
| chip_sw_kmac_entropy | 96115210434050097358678388289865619476224159914735481393998055064808408929818 | None | ||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 19905282731617413894015946886471546885005754909343440735070860788721243340707 | None | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 44217489488687341753301965521939867866913291685950952326527814707435579539124 | None | ||
| chip_sw_otp_ctrl_lc_signals_dev | 63748731734342087608769940022550880190408175171694941266384367715462733467272 | None | ||
| chip_sw_otp_ctrl_lc_signals_prod | 107342982658375994658745295721284783147201915616403200198448663184435926856056 | None | ||
| chip_sw_otp_ctrl_lc_signals_rma | 41495488223983435318799175948761475824858953676645414370434936479154388687832 | None | ||
| chip_sw_otp_ctrl_descrambling | 71695143280214272166420879632513236589033391931344897318646703422681715273376 | None | ||
| chip_sw_lc_ctrl_transition | 98510566570188554152546466600184831373713486186604139279768280972684194844818 | None | ||
| chip_sw_lc_ctrl_rand_to_scrap | 104094559744195675558887598597006130607942653937794798256854150171772133155798 | None | ||
| chip_sw_lc_walkthrough_dev | 29011160284633712177471187962049718106194227062909339961546920871150168400972 | None | ||
| chip_sw_lc_walkthrough_prod | 95878118959945626312795317149568418109817177484751050175689384380982247095092 | None | ||
| chip_sw_lc_walkthrough_prodend | 24873426192805288155030370469560081806893221858597042044042892667095980730221 | None | ||
| chip_sw_lc_ctrl_volatile_raw_unlock | 92598676983181317642764323345697822575319535787431996265634771984287740054090 | None | ||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 82810409685979810540279822352753994217038080381039553928658125885049049202981 | None | ||
| chip_sw_lc_walkthrough_rma | 62386560089348708764274263418887316975036998442973586532493373086644201354786 | None | ||
| chip_sw_lc_walkthrough_testunlocks | 70175463462349700889584144274332711350599396939671829327624627338373142953747 | None | ||
| chip_sw_rstmgr_sw_req | 72690341017582270096962828350719943041648155840333433394769778638330461346162 | None | ||
| chip_sw_rstmgr_sw_rst | 46684897629662362590854779964259119525787324881617358394375709619390943279325 | None | ||
| chip_sw_rstmgr_alert_info | 13487296577763786333573288130169151538888056133713215572041917177236152676540 | None | ||
| chip_sw_rstmgr_cpu_info | 17822708151273375175310530121772297885298391431589154627717570136445946802612 | None | ||
| chip_sw_pwrmgr_full_aon_reset | 44140277147612082399748465023083860597297137160752663719302574709309271543112 | None | ||
| chip_sw_pwrmgr_main_power_glitch_reset | 10214910738052716476794791933664192765456725645417251969564617210775570320075 | None | ||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 92489077992453976881808150425041982089158705946311398125282692603975408037807 | None | ||
| chip_sw_pwrmgr_all_reset_reqs | 32149051516445155197017851743764215958875408447858475615227563500431493238199 | None | ||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 110081466771686062131977113859736540566368143548909430484207272803790032538598 | None | ||
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 89107763770700124854649932300183456826640288257609807323155550976170098442425 | None | ||
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 101647981380177035665045437586855649868603758067867358853079601417518620467807 | None | ||
| chip_sw_pwrmgr_deep_sleep_por_reset | 45734067145660788103459856477616726896323684468378011944298372878970870988792 | None | ||
| chip_sw_pwrmgr_normal_sleep_por_reset | 96941743472000637372629282649790840156541089519649303556356946214197072311138 | None | ||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 105391186961072744766420071281810789326216640147888297417393397504031134596748 | None | ||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 104218505913952152253232595160622126361834243255130466170500337085660878758205 | None | ||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 70154037966819644443126090082959090271202546576131228066894934240664915068367 | None | ||
| chip_sw_pwrmgr_sleep_disabled | 65509986008632608399164904631662663355891393625479910478393212601585361788564 | None | ||
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 48830291519192630080848447427974885787652117960504652553767796981165037690377 | None | ||
| chip_sw_rv_timer_irq | 67674327508037144015861375599043809628547455292472092850021362076444847618224 | None | ||
| chip_sw_rv_timer_systick_test | 3828585493087804306028204419779043957465418906303750159222231243047249643732 | None | ||
| chip_sw_sysrst_ctrl_inputs | 92112994013585775640367343142452296367683232682155300354590861294649728609984 | None | ||
| chip_sw_sysrst_ctrl_in_irq | 412767580359767661300124885592965742833625833824932334050741025392441073890 | None | ||
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 35065114582365562179393360702717313165237308019656300606188766938631059957625 | None | ||
| chip_sw_sysrst_ctrl_reset | 94454863448855130908472424654048876086454774259524862038724358365636816543995 | None | ||
| chip_sw_sysrst_ctrl_outputs | 22449860838680180357085175700819969703389867092892044803837777581221796045819 | None | ||
| chip_sw_sysrst_ctrl_ec_rst_l | 84664779446676497496518008385468139153495324755927794785315239309540843093661 | None | ||
| chip_sw_aon_timer_irq | 76167522033761498382074170901594737958627411838932917383673526484749416414320 | None | ||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 56873193432430147485929869093821329435795820511581827818131884492553411973599 | None | ||
| chip_sw_aon_timer_wdog_bite_reset | 34850475452951804198174395570678599686483798531915638584511295743567579910437 | None | ||
| chip_sw_pwrmgr_wdog_reset | 90093805330039691541517337644762659830493814310628032915852252526101673748471 | None | ||
| chip_sw_aon_timer_wdog_lc_escalate | 59045271081370174959228210907105191748479896449493947919078903519436401167153 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 115697083533463510728571158515384072928264754496675415687712710490796834116488 | None | ||
| chip_sw_otbn_randomness | 92630210158410594064607021583265762844124119425793600745854642325702446427421 | None | ||
| chip_sw_otbn_ecdsa_op_irq | 47431293683833329265319019542203089282823159709965184406548684507621787271965 | None | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 96187795367416808408991868742939700670256144911860983631506853609737407829479 | None | ||
| chip_sw_otbn_mem_scramble | 43358750584623274770243749814715672478809241303391108353142058401918860866576 | None | ||
| chip_sw_rv_core_ibex_rnd | 49607508020408123737692148610969339946742205848381176502149353885044079651330 | None | ||
| chip_sw_rv_core_ibex_nmi_irq | 94325159733165057522252221067228711749491626744346995000251802126211729598573 | None | ||
| chip_sw_aes_enc | 34363101392328357410023453140481397680428132800166017618414775800164590563575 | None | ||
| chip_sw_aes_enc_jitter_en | 106048724336397321274383595460112452971209747192088201310925861568355809349988 | None | ||
| chip_sw_aes_idle | 80499918178841828775028645107940617159059673645733606477236559035108022328152 | None | ||
| chip_sw_aes_masking_off | 86909449758269263953171805895472201378887321008362738350470010661893934889052 | None | ||
| chip_sw_alert_test | 29959439751396163286873060452713896643014403125912592569277140285045836536826 | None | ||
| chip_sw_alert_handler_escalation | 53191422916919342296952187719334434905828921734363095466961532774681900926856 | None | ||
| chip_sw_alert_handler_ping_timeout | 19891893150451548965498513903439127533812147944608492055784242863215198869265 | None | ||
| chip_sw_alert_handler_ping_ok | 39012089907424383721717606556327469740815471897733654645691019848321929356004 | None | ||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 86984337665053930992917683444550820425931273454226606954868294335829474139395 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 22371010025640839845047135994497430366159905680176989621548718879881326220950 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 100435390708740929257811152262995928538543231941319334203364872496723233823595 | None | ||
| chip_sw_alert_handler_lpg_clkoff | 106083083157767889728303807954423153161763284283210668354760530712198683960192 | None | ||
| chip_sw_alert_handler_lpg_reset_toggle | 105672540663006959921161087702488312497313991930533500982219690466985497063431 | None | ||
| chip_sw_alert_handler_entropy | 40212694785166851532260276090653154300127865240667692511584737832270100135284 | None | ||
| chip_sw_aes_entropy | 70220662729472791756379261920582963867659385749098928626415507075730782380448 | None | ||
| chip_sw_entropy_src_kat_test | 46254289963683702153621156961081791264910833883998004757689379206442728352501 | None | ||
| chip_sw_edn_auto_mode | 79966316666503730804343588717108437028277690258918918078363298676194750020359 | None | ||
| chip_sw_edn_boot_mode | 68034717222068504371135371075927501102220607909516209032156113466386991841558 | None | ||
| chip_sw_edn_kat | 49226367863390431260518750185176328951088384163304901799654646924836161429237 | None | ||
| chip_sw_edn_sw_mode | 51381189895613031812081138577987713944013840387766566785742719749517315824600 | None | ||
| chip_sw_csrng_lc_hw_debug_en_test | 35722428414078733098903812359200527614138913728000054052081690330013499722557 | None | ||
| chip_sw_csrng_edn_concurrency | 46375136584145016612068209534820279808955549781282036890975218177067110252438 | None | ||
| chip_sw_csrng_kat_test | 12049964658260049375922270895505391378987560598077644747698680851135512441556 | None | ||
| chip_sw_csrng_fuse_en_sw_app_read_test | 64002833694188650969011447187632437573253213154187915811782935176277841913082 | None | ||
| chip_sw_entropy_src_ast_rng_req | 61410491437884630632181696870911928204846101749669039187264662966950846977324 | None | ||
| chip_sw_entropy_src_csrng | 50825212213165065663352106036473748210970532147097301977838685692304012094320 | None | ||
| chip_sw_edn_entropy_reqs | 43058924693953961361449244763764010546801174245298020759454313577034046949262 | None | ||
| chip_sw_edn_entropy_reqs_jitter | 14575064883798205220872818244625803799383123153400400395734686079746405617984 | None | ||
| chip_sw_hmac_enc | 89811953263899776165931341958341994616337384421640449951543930907130903386881 | None | ||
| chip_sw_hmac_enc_jitter_en | 114976641478492843926983725536241724505833619924812631728165769258288788345753 | None | ||
| chip_sw_hmac_enc_idle | 67333094981868224046398731702667721115311881245299317539592793943876393889680 | None | ||
| chip_sw_hmac_oneshot | 76420925884595809041592675728015858572870320975489640887476952041785259376063 | None | ||
| chip_sw_hmac_multistream | 40213738875006994131639616370134596043541000869210294655988711848993467891334 | None | ||
| chip_sw_keymgr_key_derivation | 34673183430429338456339395358210897039127367718315638835925003694725598441035 | None | ||
| chip_sw_keymgr_key_derivation_prod | 59651008989934305728002873770726612929755016184884006685309170534286144726152 | None | ||
| chip_sw_keymgr_key_derivation_jitter_en | 59731822779856483684014005021495780655984698387587338662609330742018054425562 | None | ||
| chip_sw_keymgr_sideload_kmac | 28479922249689173842619361316719846590913848896205985798689523605813029971300 | None | ||
| chip_sw_keymgr_sideload_aes | 108578147691357558399514363091511267826549037888380364546934119041143438373545 | None | ||
| chip_sw_keymgr_sideload_otbn | 74152784619297384224235160087520314659108416627597017388909067697556139101244 | None | ||
| chip_sw_kmac_mode_cshake | 34073319489742685971857669926767192583084331877053296677499952455333396062800 | None | ||
| chip_sw_kmac_mode_kmac | 7197915864992644291117073982120166335097753487645135159546597884427012626970 | None | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6243710763738408703651784826815386218485092386232798740580677507283406861205 | None | ||
| chip_sw_kmac_app_rom | 65909796487183347783309261609597488447446332934830423207528910436835338796132 | None | ||
| chip_sw_kmac_idle | 106489627846414275246331908957082511425299673098820817756503321573594814621861 | None | ||
| chip_sw_rom_ctrl_integrity_check | 28254762437388673798755781097864548969319171578455419209861311136106226626299 | None | ||
| chip_sw_sram_ctrl_scrambled_access | 74188334889168318787324580890634559490294176895497150236239728928379110460396 | None | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 98552990064846359708239401212382978741648402701909421924656888686388102804859 | None | ||
| chip_sw_sram_ctrl_execution_main | 95883354826638786860393916651197399933597120318438429038889905957189701809990 | None | ||
| chip_sw_sleep_sram_ret_contents_no_scramble | 106093020498843624532768513223409977203414261710301611874842134085440883434367 | None | ||
| chip_sw_sleep_sram_ret_contents_scramble | 65792451622138723083529832476787799387736372480110886352528035364991546714150 | None | ||
| chip_sw_sensor_ctrl_alert | 73995649929829870830807461035492099330742037871329085226588492803331520668726 | None | ||
| chip_sw_sensor_ctrl_status | 34404531651516095465935154542686849109634340717925286440926513787116731559165 | None | ||
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 44548011522799557178733678249884792950669062226148210984026105840363502865934 | None | ||
| chip_sw_pwrmgr_b2b_sleep_reset_req | 36129367030411402898995684200323712192186976592745106431025742073211023370279 | None | ||
| chip_tl_errors | 43839472354767479528859748941187346809016620661624362197464487415304287879215 | None | ||
| chip_prim_tl_access | 11291044126601209546128801922904472297767949351449071812736505842646529760476 | None | ||
| chip_plic_all_irqs_0 | 81885892895268720466717143502501365092591203144868223626147146913898934457663 | None | ||
| chip_plic_all_irqs_10 | 91836206876785379334136272973615348476547775947530058588378361097357717323922 | None | ||
| chip_plic_all_irqs_20 | 53001080186981063342039933014277930603755981538895690988086035673243210170355 | None | ||
| chip_sw_plic_sw_irq | 108873651538091935399269910134973256445998937802974630332327107858441661574512 | None | ||
| chip_sw_clkmgr_off_peri | 110659827959754763083748709159178904270609691159857094153061159457474929063130 | None | ||
| chip_sw_clkmgr_off_aes_trans | 44036972913944558726294384569034170538611999432900455469008829307473517139686 | None | ||
| chip_sw_clkmgr_off_hmac_trans | 44971001244547658088405845264785683064859677736511272298468526561533132901061 | None | ||
| chip_sw_clkmgr_off_kmac_trans | 112557782485864903537388259097504475086286181007920007730414238957054153851031 | None | ||
| chip_sw_clkmgr_off_otbn_trans | 6541763300283667993957413600693718044380355449033616364327226770101250984451 | None | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 26800494593590839811932598895966795062782968389508030209872858484348288326969 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 71855616908747583982471729517557401526549676948233375517871500648998816931494 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 81203202562337690615438167768147570403365956618976173030619514478871854836192 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 63978053625977115351256055278421948574516263451506370121309192458371214939353 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 77555432132516168681423224613062426582761900550738867674197702054172529120221 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 97723208939290037388422586778274417581947665445863100691468222209905764669355 | None | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 104152919909871405535847212014940420063732720909617599006453269930367514922496 | None | ||
| chip_sw_clkmgr_reset_frequency | 96294827686590000565791389538443391049814178028616259760569381076319844549561 | None | ||
| chip_sw_clkmgr_jitter_frequency | 1584183353882056541382698895246962341275581739342016389262459308485169075174 | None | ||
| chip_sw_clkmgr_jitter | 19586900175222264653812019765475754222326769378349520849755919230442930977690 | None | ||
| chip_sw_clkmgr_sleep_frequency | 113876095915229143691696017777030657153095604744758251707055348905075185820751 | None | ||
| chip_jtag_csr_rw | 106130096923904667148791065428674245181692681377855094700308101042642000738769 | None | ||
| chip_jtag_mem_access | 23049426013003030865119325444714868043776501372432453569017718572640596634018 | None | ||
| chip_sw_ast_clk_outputs | 25476357337532288378386096825742219179767359615764861650478240906518729143670 | None | ||
| chip_sw_lc_ctrl_program_error | 111456784714101506502599418150197322746779546728387621075309595049683248623658 | None | ||
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 37616365794633132841248224983015961220609960598610765646837043905090211045392 | None | ||
| chip_sw_pwrmgr_lowpower_cancel | 72091674096145449367444497906457055849869072642057268689069507484993340426113 | None | ||
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 24865212027161658513775990649279773844111040068223939191320266803752133978958 | None | ||
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 104667866307817709785693294500307827114184829755700546299039970205225510977774 | None | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 41378965608610789172573544254485380755606877487566200993509572990556753275874 | None | ||
| chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 60825546509406303782747484767734297173677045015226991358754491201675021584422 | None | ||
| chip_rv_dm_ndm_reset_req | 90588619589056084411194339092538669035859263451430962751498340856133220680936 | None | ||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 39888402722327056477241307633003690532215005862913042686586565172665204612222 | None | ||
| chip_sw_rv_dm_access_after_wakeup | 25894070366479853037303384308570645085049912961863102381143847265859196661794 | None | ||
| chip_sw_rv_dm_access_after_escalation_reset | 35225575738189147841973833180511947506899670165843845917401965611710113247929 | None | ||
| chip_tap_straps_dev | 89788594315811475700559332271695873884486142081551682376373141713725684503149 | None | ||
| chip_tap_straps_testunlock0 | 93117674267721634192933488825385143611630744131984320238344239136336137563930 | None | ||
| chip_tap_straps_rma | 94746911783115858610136874887525178521320322407339385593399231475778623178542 | None | ||
| chip_tap_straps_prod | 57327886339315390316582039769771265192231659204769590043494550047190340884546 | None | ||
| chip_rv_dm_lc_disabled | 80841977280760743029209194392111772255175188598440429093251294167049307007269 | None | ||
| chip_sw_rv_core_ibex_address_translation | 58777448226911388957767660415564093327000842699482460974902550012408019703442 | None | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 86746512523939868503132496843721223096233449070321138388833166191773698659268 | None | ||
| chip_sw_rv_core_ibex_icache_invalidate | 32664178027677780418620955605686947863097462809683185012641819332776555841053 | None | ||
| chip_sw_rv_core_ibex_mcounteren_writable | 83887047877807582708749079669806790293154431594453759459247760352678059335572 | None | ||
| chip_sw_flash_crash_alert | 16403202643138356029771895383071522197994499120338260688791981689101694849955 | None | ||
| chip_sw_flash_ctrl_write_clear | 84259758305269877095656422446261822896531334757533364872050367493276374263329 | None | ||
| chip_padctrl_attributes | 115628656480288117822325544153155623678410555578494168272145423719116334716629 | None | ||
| chip_sw_clkmgr_jitter_reduced_freq | 92326989830449935707423655895751950369249576141440850204718826350673811538202 | None | ||
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 23383502843801102944140016303580716247728682149104163519765888881324871568547 | None | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 44774174957009337345624820950991287592862011604961035416187722667831432520425 | None | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 56685513857323152266594080160525667668112471843310432389731234214510631808294 | None | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 25536517550286946561370182854904213407499984302792520971171267525266387737843 | None | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 16070068386244609065653776868707076446201956148610059481508690914148658471076 | None | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 34028830955126303896132983342676765309655577457651228227315327030643112739431 | None | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 29545537278548292849176787809215320679068054254109411109644290183617019937736 | None | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 61115313358854077037953192892786981355292328667486953661090438652713851274684 | None | ||
| chip_sw_flash_init_reduced_freq | 69697301007774431277417127968176024954357431200765998681494184227597394635501 | None | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 53504212934942261681739797703439861206267280945890700038677975013759552455031 | None | ||
| chip_sw_power_idle_load | 65965968044534333694857118381176117982114284184985392798121238708767107373000 | None | ||
| chip_sw_power_sleep_load | 53889718729942668910163022161617181073954189166626614964757216774355406664203 | None | ||
| chip_sw_ast_clk_rst_inputs | 81337946806417010239487893388253938655609643602171295415378800290741786410708 | None | ||
| chip_sw_power_virus | 67002920995130374475500683956520025566759300676353996858625659572487235140913 | None | ||
| chip_sw_flash_scrambling_smoketest | 38094167540990149187898178176977649450502146807543273699519146608218418957334 | None | ||
| chip_sw_flash_ctrl_mem_protection | 52458782170925429457727426121861878636516141336066147931130122001017532484592 | None | ||
| ate_bootstrap_flash_erase | 46345598263637345922342368024489885789112546207202200923071620202936232034927 | None | ||
| ate_bootstrap_one_frame | 15107466545574011967307505431633568471645827341957611620755018519899734668318 | None | ||
| ate_bootstrap_disjoint | 44136033705390049201577873829987214251231349242496134638993664820110408578022 | None | ||
| rom_e2e_smoke | 44071757699189601760984481315478971666885475505870171640889909406249950339432 | None | ||
| rom_e2e_shutdown_exception_c | 61747338295306397513141687114660827834685946616366999413983422268434154521464 | None | ||
| rom_e2e_shutdown_output | 106778908409882259269953245785735982809589233413654032943402859883648070919029 | None | ||
| rom_e2e_asm_init_test_unlocked0 | 53467434975003455599605419059149734539872332845863237066933370494063822098778 | None | ||
| rom_e2e_asm_init_dev | 67327637317917011155138592698554903557680514593142020872772739605364875433010 | None | ||
| rom_e2e_asm_init_prod | 49891367663475273715348921052038785058849803088673942186709001695812197451600 | None | ||
| rom_e2e_asm_init_prod_end | 53006605958785574880727033661912485863900139679990786340971236865121734964702 | None | ||
| rom_e2e_asm_init_rma | 63228603623864867353527677668589956429604237909489653785107766992894638763644 | None | ||
| rom_e2e_static_critical | 14345719486798438088918265778681717057828551193064218475573214528230492053270 | None | ||
| rom_e2e_keymgr_init_rom_ext_meas | 26130342669287690818025274660351187116927436012363829649738162586958912833541 | None | ||
| rom_e2e_keymgr_init_rom_ext_no_meas | 75308422409619988223962000534136174695461428287931426479476039904279274589795 | None | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 50711567228936600936070970737027408133119458028535100662708524021625462371856 | None | ||
| rom_volatile_raw_unlock | 32670897322230003510650792451154363450133551440499737609547099655000561881857 | None | ||
| rom_raw_unlock | 62470044170659200261568528023355995798752282577888715516582183993732445654632 | None | ||
| rom_e2e_self_hash | 58643465072192721578706545011159545646026589879878174721980282313585909638178 | None | ||
| rom_keymgr_functest | 109860294343790199413145017907082164679078776077010739243795345083559829510111 | None | ||
| chip_sw_aes_smoketest | 45656668538041617142394139433035054348247283790507387140291597492704017336958 | None | ||
| chip_sw_aon_timer_smoketest | 23610229053287813552809343514051844500767827881416888866584270649290386758889 | None | ||
| chip_sw_clkmgr_smoketest | 115592608764672618478297097563238480834006166969517188407810454730642156500205 | None | ||
| chip_sw_csrng_smoketest | 76766462244525193369834180244000649272615211362496729106916697783711989688528 | None | ||
| chip_sw_entropy_src_smoketest | 29293270246726929087613620028529720425651177497299596184049004081124720998014 | None | ||
| chip_sw_gpio_smoketest | 92489535622468311966427758128988121170955934257133290294749564315938236664292 | None | ||
| chip_sw_hmac_smoketest | 12428145146320745619636395651985078148949690613566490090656695718858904543154 | None | ||
| chip_sw_kmac_smoketest | 10123473521318853574430986566769508084085606793980604708515422226232800626485 | None | ||
| chip_sw_otbn_smoketest | 55152641474965694412076193421427884462114272720762958485420457265530551922422 | None | ||
| chip_sw_otp_ctrl_smoketest | 63298755484054300793893546193749611611565894109132263010959381337553779788086 | None | ||
| chip_sw_pwrmgr_smoketest | 97402615681308833960282494556365259147431223789369102084277649090573096687193 | None | ||
| chip_sw_pwrmgr_usbdev_smoketest | 51565103357553137163196706904275752692291386055719063944257607677784419090454 | None | ||
| chip_sw_rv_plic_smoketest | 76932991208669939866336023743506172991761983716257644237698342837896230009327 | None | ||
| chip_sw_rv_timer_smoketest | 57735142101166458296867846485245213509778312054546970708046619136959520854130 | None | ||
| chip_sw_rstmgr_smoketest | 13022859301415042531600846292758686549050944665707114809555742067119025870056 | None | ||
| chip_sw_sram_ctrl_smoketest | 93240903062957433232019025661116208301486240647005608105881857324111601972338 | None | ||
| chip_sw_uart_smoketest | 49375211643558024672156962867039562733878468791002914719837148800133207506583 | None | ||
| xbar_smoke | 85161354403020674565952560914187134439318055138079858791554676440339143171335 | None | ||
| xbar_smoke_zero_delays | 24965705502229724379590346268001460558940598328970703856353031237378482833362 | None | ||
| xbar_smoke_large_delays | 52702556527019817619090678122959661423425241235472259963279124349767330624576 | None | ||
| xbar_smoke_slow_rsp | 89913068580879737979746289788666484053743108248665500385087721832783566722941 | None | ||
| xbar_random | 2824520979516469335544207736757491249109034736501931686667502508198897405873 | None | ||
| xbar_random_zero_delays | 110352730518173002516485676878411219037055277134277524472726879721889041182704 | None | ||
| xbar_random_large_delays | 78300987207914538527391146196333853381907299161806136922613043949568529790950 | None | ||
| xbar_random_slow_rsp | 42139021222555995976969394897693758719250422163687115331788940960500995388666 | None | ||
| xbar_access_same_device | 115610127327983785107603515006925457299356048780848435031575453641562849538258 | None | ||
| xbar_access_same_device_slow_rsp | 23832860985941404536494765413103850771967004152687802482280309357427736761582 | None | ||
| xbar_same_source | 85542638957146339433009891077798861808158809111768478045622300355271885523407 | None | ||
| xbar_error_random | 104326508108579467262353301774804556681295745120727260037068488357804545129666 | None | ||
| xbar_unmapped_addr | 87352361140723188420519365028553839934853462140083831794154164573996398026717 | None | ||
| xbar_error_and_unmapped_addr | 71545192473730324251829919176702617103496956128248355886400489354889439419511 | None | ||
| xbar_stress_all | 46561117746095512068742702248325337304182919333656126661015032508377776059589 | None | ||
| xbar_stress_all_with_rand_reset | 31001198379739023636983516104859811289634659175794595483447878866939774109641 | None | ||
| xbar_stress_all_with_error | 30602154269913350776567090593231051663168768060456702607430833106110326067502 | None | ||
| xbar_stress_all_with_reset_error | 8711215625161677091115620250012479337911384293781193600470144218421415889807 | None | ||
| chip_csr_rw | 93600852429979214978560065809292799451662747880619571883712648156775581626140 | None | ||
| chip_csr_mem_rw_with_rand_reset | 96983539560822873901409274180846987952064792924797126625351123570473291565615 | None | ||
| chip_same_csr_outstanding | 97171472419467475638894292614618730992938719170688056223432691342353776610923 | None | ||
| chip_sw_all_escalation_resets | 45988948621325539975212254099463250739602275777058019911518884317087432366838 | None | ||
| chip_sw_data_integrity_escalation | 96240982531214824146166364030819820343187054794572791583910764645938602430418 | None | ||
| chip_sw_uart_tx_rx | 64248998108214110863532875513768887626692744330736854925269025308704466604322 | None | ||
| chip_sw_uart_tx_rx_idx1 | 64742097038421028405500858201510795878793121496896769727972686057998106194308 | None | ||
| chip_sw_uart_tx_rx_idx2 | 30406129199037731106769548851796503042200572073269949843057127270929410253037 | None | ||
| chip_sw_uart_tx_rx_idx3 | 65680831280898049183380275872664657456606976295136875900469386674556294429851 | None | ||
| chip_sw_uart_rand_baudrate | 60491071533407387929649263662734433053989478236109996616279104981687887527430 | None | ||
| chip_sw_uart_tx_rx_alt_clk_freq | 99505680592441728310923729524103058592302041588889867374131209858009742745856 | None | ||
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 114218870999555326934241432303997933941877612117047453282013062783285757256148 | None | ||
| chip_sw_lc_ctrl_transition | 82809851167256382501217099957968707635766467914144991347672789248961663311646 | None | ||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 11057617986629433008651416612163301666901096948946117396393622389635963737609 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 34166980022775406674987141400235002276413589036662389211733187881417487678912 | None | ||
| chip_sw_csrng_edn_concurrency | 49266406753713981598331004636576988953267754157703681650914059096079561278560 | None | ||
| chip_sw_sensor_ctrl_alert | 73433205410263846699699555182661069487023529016556205076499199540744419834232 | None | ||
| chip_tl_errors | 83824375543159894125613279432555415916276989759113518513591721588083296063219 | None | ||
| chip_tap_straps_dev | 86184776708019769804364016646112240293469638238594771364292222301868823902370 | None | ||
| chip_tap_straps_testunlock0 | 11298279282719681798066602820930569187354308916178414612899549384813005341187 | None | ||
| chip_tap_straps_rma | 35612969805501858160852823047247310297352520668764945270706193081568812177148 | None | ||
| chip_tap_straps_prod | 18035048197156982834449493313780340215923711055950982024500728405565780075128 | None | ||
| chip_padctrl_attributes | 39573540047445411291368521413536031808933986722894167696415508311422925674090 | None | ||
| xbar_smoke | 77304619875324634827233899071193155678325462826619361129019125004776174390128 | None | ||
| xbar_smoke_zero_delays | 82233771776569052043810713363691205998964707226412944111472964588862497347435 | None | ||
| xbar_smoke_large_delays | 60381396957568907731906398550287677710747523763825493886545961724607150014335 | None | ||
| xbar_smoke_slow_rsp | 46297129828142393702835391515961716711215167150254343381077389717126079666709 | None | ||
| xbar_random | 67061569384771547964864069674199749424568824989520264150145275572231420504364 | None | ||
| xbar_random_zero_delays | 74530964394348441247700304602653528572657935947254551630924218635611416184565 | None | ||
| xbar_random_large_delays | 108744749429498854571504425446842474759761726721723621831391412782862740623528 | None | ||
| xbar_random_slow_rsp | 91762354846564184546415584498678491477353382675255496724928394590958431141785 | None | ||
| xbar_access_same_device | 72532078863393170943232050644190599211929031004055943420783222791283245024341 | None | ||
| xbar_access_same_device_slow_rsp | 2585450095666657645009963690992690342446748570065794712089511573408504584701 | None | ||
| xbar_same_source | 93714926970983881042206308303283035884930677361686962915373059735558533802234 | None | ||
| xbar_error_random | 91614873214070019400132224324478311247590216534990061803885738759932155267107 | None | ||
| xbar_unmapped_addr | 6780370347818341933087899098448024151179031712433336922410230660249874573972 | None | ||
| xbar_error_and_unmapped_addr | 102946708670734860061902787113272679470320957587282359526572048449621651619084 | None | ||
| xbar_stress_all | 72871657693018526362505601198432204911550572720794927301582772465713801128322 | None | ||
| xbar_stress_all_with_rand_reset | 6895834615520766032252973444623721699554746905375734271418096292588273206634 | None | ||
| xbar_stress_all_with_error | 36738392535715090312151811771062332979479047033463499647044123852748941469880 | None | ||
| xbar_stress_all_with_reset_error | 92287431754811900850511026559686477351259852881757301039874243468822648974909 | None | ||
| chip_csr_rw | 110303376750499781389086608914997518133045274545234628134073998037558147885382 | None | ||
| chip_csr_mem_rw_with_rand_reset | 18920009643314151665183634793588479230419291752384360938045923851172413170210 | None | ||
| chip_same_csr_outstanding | 70121912390937007754106015248102830916488066531677191149351949661305275705061 | None | ||
| chip_sw_all_escalation_resets | 76491066237886412946716604009724743366113366436025614209218406130826364053728 | None | ||
| chip_sw_data_integrity_escalation | 27657755698889335572479540894659466633963064477843594802502475433281238664687 | None | ||
| chip_sw_uart_tx_rx | 10647925753111371053145000626775166782067521164164961603229536221689391064077 | None | ||
| chip_sw_uart_tx_rx_idx1 | 49004641348405054888771219450189145066834612054035849221521633135593057828333 | None | ||
| chip_sw_uart_tx_rx_idx2 | 1216422784149755964447174231539015489742603823103827639254580906938605982389 | None | ||
| chip_sw_uart_tx_rx_idx3 | 64547095812242997677690505941466132706912446663084746374201473610979330752609 | None | ||
| chip_sw_uart_rand_baudrate | 1611680760410379670768215022432400175032147507355109741572599322439328384581 | None | ||
| chip_sw_uart_tx_rx_alt_clk_freq | 89759580205344637341371080915639622365055127484037540208999984095107478483873 | None | ||
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 74952703884623776271857945316662173144720943549830597269408971597834156387886 | None | ||
| chip_sw_lc_ctrl_transition | 99939065480205404821400160914126110794864619544092263038577008038138292769590 | None | ||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 106323007912243669536949378035069799984751132782899266072584157905201760399763 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 114531482766480574068161340955707418280644484289904856947850733512333954135061 | None | ||
| chip_sw_csrng_edn_concurrency | 90276104852908380259169306766361381490703259628407015418517682061406763179657 | None | ||
| chip_sw_sensor_ctrl_alert | 94326274463258332268006767907877749748778649487567747634082315499262738222909 | None | ||
| chip_tl_errors | 61451347524115620128014131611473151242006938173750280806260767173842070201839 | None | ||
| chip_tap_straps_dev | 88209782208722523371555762609509112456814344190069032264764805801094743184419 | None | ||
| chip_tap_straps_testunlock0 | 94981009865543838341782368785803086152263312696256962234725178883064276344439 | None | ||
| chip_tap_straps_rma | 28447495959904225918287280070929512339503550854078224144544315700538889716398 | None | ||
| chip_tap_straps_prod | 57767445623521674463336535942644568404616741348898773189198076241000521707868 | None | ||
| chip_padctrl_attributes | 84403660708214353783846219023652041823355835026638860953799202659371897936652 | None | ||
| xbar_smoke | 90576263157818380609564160309476260446138766170574984890049609089912630591157 | None | ||
| xbar_smoke_zero_delays | 71773054425174263736189195465744341611807291628990035366491843540670307865397 | None | ||
| xbar_smoke_large_delays | 3872529053352020397162548686059373320688616357442608136369006241517785314843 | None | ||
| xbar_smoke_slow_rsp | 47048121645502420220467839916847439814028688686914392099886376523205768491679 | None | ||
| xbar_random | 66699163305452669386811024598506141031041105182170501892420718236498824373306 | None | ||
| xbar_random_zero_delays | 100917087493598099816488903399681570550096517468580407376692763032071671340628 | None | ||
| xbar_random_large_delays | 43501316778107590068883920003804684076636712600598290028560135885310872505773 | None | ||
| xbar_random_slow_rsp | 56372051267976494441187310050057703027401396968914584069416883177318172916151 | None | ||
| xbar_access_same_device | 93297754423160198164708646994896754611371010468131795907242303016355905497544 | None | ||
| xbar_access_same_device_slow_rsp | 28087292045111180227888425055688290876952196809284983528481458266895425319348 | None | ||
| xbar_same_source | 70249087036176787335006274986222954294226107771598187389547945499206496183014 | None | ||
| xbar_error_random | 35643476136661424150191630768552239934178264547204195402475052195684839383935 | None | ||
| xbar_unmapped_addr | 69220047961805361626709173967133909494297451243023995522053039100284658924517 | None | ||
| xbar_error_and_unmapped_addr | 76118282599299049128934569310965329200445884516942338182963344053406822376555 | None | ||
| xbar_stress_all | 8633320301131109279682632229360166885106989494378906232324019127455189790464 | None | ||
| xbar_stress_all_with_rand_reset | 10107915663577230937650621097546336144754636649225950054039263989117546105339 | None | ||
| xbar_stress_all_with_error | 91204606090429170388804197770047661547259555197962154407632236480666727818296 | None | ||
| xbar_stress_all_with_reset_error | 69277087722774970118262114806737905667642117747188555445015941987304602052442 | None | ||
| chip_csr_rw | 41711175648308916120167807768740171678066949368251215247244295526648280129125 | None | ||
| chip_csr_mem_rw_with_rand_reset | 1010654291585913423415699967899665237827024050235482558451926329908349314613 | None | ||
| chip_sw_all_escalation_resets | 106547224677735604630794757040517143214382239500261851172329642780098779305598 | None | ||
| chip_sw_data_integrity_escalation | 100579102703453823376135082231558810643292437676654348370818109804080556951507 | None | ||
| chip_sw_uart_rand_baudrate | 75948485756164281037293090151955830525627412677890269602578561475903705192464 | None | ||
| chip_sw_lc_ctrl_transition | 105214007678608827233714196198207522182095724140466152904842290870777021663063 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 2047506677889232696941260019207271794750450444307660524157062518419309247271 | None | ||
| chip_sw_csrng_edn_concurrency | 14584827158923009418153472317449155910760493861031542285862699380747272334556 | None | ||
| chip_tl_errors | 72737608503700312038840880374456920582419532560852058115291185560518693863327 | None | ||
| chip_padctrl_attributes | 87529227738854662678080153388658544547876830608175119563879151960769694115835 | None | ||
| xbar_smoke | 69224682820976509041813345730573264681846180212659891694320635468431115213483 | None | ||
| xbar_smoke_zero_delays | 63381100574554175550399734365114718498316405435106448830691893148051015536312 | None | ||
| xbar_smoke_large_delays | 41453788399495884819488896037605412989339050037309425403867884444108234783022 | None | ||
| xbar_smoke_slow_rsp | 87086585797535894619155635299982415004703242070977924664984614718863491334117 | None | ||
| xbar_random | 104999098004712115526564883269178795641332920343316244488394375799053423444188 | None | ||
| xbar_random_zero_delays | 107385661093180586275524459809481791536062373387001008165749336381199972461036 | None | ||
| xbar_random_large_delays | 106645764223325334074962107962253318593159543640255537555125539974731943137779 | None | ||
| xbar_random_slow_rsp | 36057489798063164275198650105462561952419072902814505746212858325158555453332 | None | ||
| xbar_access_same_device | 86051572955621192141409692176692334576791140496843307972682037608704231415319 | None | ||
| xbar_access_same_device_slow_rsp | 90679881995519825210062057573583373461690182784227437808593922068372151979739 | None | ||
| xbar_same_source | 91200576096988330100094731478633739710978055180327612712735706499812396249419 | None | ||
| xbar_error_random | 35904263613902536475209060619199008931057625417474109493072463249769425667805 | None | ||
| xbar_unmapped_addr | 47667894665961076874902518505558154128736722307997941536386074929244165094070 | None | ||
| xbar_error_and_unmapped_addr | 48645468206975784207498892373968988568600781573459959409706142103880665814611 | None | ||
| xbar_stress_all | 70926849739131266876372831628695078551108709103778970861186119112657346030038 | None | ||
| xbar_stress_all_with_rand_reset | 68501613446537645905375042960192078737470465065767231073747443201669039771358 | None | ||
| xbar_stress_all_with_error | 55633293905484041408535388315071566084247123994486718918416722908467717129995 | None | ||
| xbar_stress_all_with_reset_error | 21572257912205942679426398725740794191845446942833989620349952927627981314314 | None | ||
| chip_sw_all_escalation_resets | 35451243522555873478449671177360551590908034020793106980833261281599155628809 | None | ||
| chip_sw_uart_rand_baudrate | 34697904784558211391406241776216510104804620933802962023736090743181079568440 | None | ||
| chip_sw_lc_ctrl_transition | 50438614480755865237387266233695514125868387798209182198492167912332366806435 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 52136422981013545215719949647103659939759753477527696164170399934083987412346 | None | ||
| chip_sw_csrng_edn_concurrency | 55350840307552273669296392784660461734745300906856153248245685191323073259165 | None | ||
| chip_tl_errors | 38448120326822495480688689783496037622288263146174931856332333399177567769403 | None | ||
| chip_padctrl_attributes | 106085587762891758758000310624248603467177929992902293742111820552171642623262 | None | ||
| xbar_smoke | 104949873807885670992931361913631344946520299787258544290632425292890797277707 | None | ||
| xbar_smoke_zero_delays | 105491531837486753941549286823797390247975208464342180307296982706861491141677 | None | ||
| xbar_smoke_large_delays | 108168546503965260232049520567419470908303019225872982361886509311443543767196 | None | ||
| xbar_smoke_slow_rsp | 4173267233859721113920525579470976414067331274108904345897019713925897664411 | None | ||
| xbar_random | 84951355991906863696813579079642134466541063577710634192420297172663516433820 | None | ||
| xbar_random_zero_delays | 27797278655781030169958967498612802867153591234888524565669753472640617916812 | None | ||
| xbar_random_large_delays | 87047627752530878550570191613832388621451053213690025784906553031150517043915 | None | ||
| xbar_random_slow_rsp | 74012614984864031285157417932227681940711892240406905247122913116178237523818 | None | ||
| xbar_access_same_device | 44153784083322814169425524247912396145189532301438880638092838281750058458792 | None | ||
| xbar_access_same_device_slow_rsp | 46930179602400971669302176595410563399365827619774629410221513686368314508773 | None | ||
| xbar_same_source | 103664781462157425429030124781679321747923914479136278346736741763702908051041 | None | ||
| xbar_error_random | 30106846116799869648714812635788539388869146354822418997324899252537166636051 | None | ||
| xbar_unmapped_addr | 17596028438399632785030379555463419911620936981324998242286030549991505245422 | None | ||
| xbar_error_and_unmapped_addr | 105973268643562281590918883882132950775171799122507403883242452593377555669769 | None | ||
| xbar_stress_all | 80621664380077442431058978440401846893898886539438131578305182175088883651257 | None | ||
| xbar_stress_all_with_rand_reset | 35731447132848621735650591949293802712960693928692469291380141913363787201860 | None | ||
| xbar_stress_all_with_error | 23172047609074557473264455939383821732583870193698230877315879275636919184862 | None | ||
| xbar_stress_all_with_reset_error | 115713692064083640117049324293134442159123431249084510666920621717561181990252 | None | ||
| chip_sw_all_escalation_resets | 44802315426348859592116919471797252062824758737047352584853942255405602119122 | None | ||
| chip_sw_uart_rand_baudrate | 51976089897023014296792858288932608155704650197907229440298995392065767782127 | None | ||
| chip_sw_lc_ctrl_transition | 89257140805138722145207755458038804710743652555122371549715578656956046515517 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 97572594726641526252330641223534259413628857048643575080245060282172209579998 | None | ||
| chip_sw_csrng_edn_concurrency | 34187515531349229554291951694291140670563266681289129095371664172108565429308 | None | ||
| chip_tl_errors | 34416222317928533509289849764900777774361590052766197987638424201892880355669 | None | ||
| chip_padctrl_attributes | 101658990848483082146388668046767628091787530697590528837500176144556966183101 | None | ||
| xbar_smoke | 107869635064077760750881797337942309777844657749966576150099558094287542916473 | None | ||
| xbar_smoke_zero_delays | 93754600791812530826978317289292341117060129084633069141775703302522578743920 | None | ||
| xbar_smoke_large_delays | 83476744529465171464369741816075870629068338662185277270314400058447224851372 | None | ||
| xbar_smoke_slow_rsp | 24765068017818005532406725469567987014907108635267728352852878505973038773445 | None | ||
| xbar_random | 7296061484576015784143695238074892988032697826826519865088562942429356416855 | None | ||
| xbar_random_zero_delays | 27843085136498587757297398434608508714265285480408917427990547924664800416599 | None | ||
| xbar_random_large_delays | 105241054482275523240959863041700752643917605107351337878237390153787489983690 | None | ||
| xbar_random_slow_rsp | 11946606103735686606353753517842241782226065208189646180108515663210803086320 | None | ||
| xbar_access_same_device | 45411612052914040950337932807831809832483133589865846375496637564082017977563 | None | ||
| xbar_access_same_device_slow_rsp | 25332410147946237602312095879407412738620435110119896910442833509910420471300 | None | ||
| xbar_same_source | 48235915361099933698855398252443134686103919823935212470875987458382958449605 | None | ||
| xbar_error_random | 57662771360902477706774417335916087443226469554328590058287790310594759107458 | None | ||
| xbar_unmapped_addr | 104539553745126995641580279277153902925754136158467130127712998198853663762525 | None | ||
| xbar_error_and_unmapped_addr | 18838821690205980843987572305456102718604420203293246128349228368359061645029 | None | ||
| xbar_stress_all | 6774827697527766542994467220174001803707592071190636260445268136178712116451 | None | ||
| xbar_stress_all_with_rand_reset | 21206878988398675272003582119124481206967442167312903061957015149694619463354 | None | ||
| xbar_stress_all_with_error | 114303020683318538895425265963878030507890880371113570766917948483979761090115 | None | ||
| xbar_stress_all_with_reset_error | 101646365612835818248127380815892761715958958788416834231344048436404251683590 | None | ||
| chip_sw_all_escalation_resets | 114270666981643050542643328174823398798780104993586669817553619506288052659665 | None | ||
| chip_sw_uart_rand_baudrate | 574263533066975389665436419421455630869855790802716467071805056630882591047 | None | ||
| chip_sw_lc_ctrl_transition | 100995677174998811580641499964219522677416076005622247479425476992856239819982 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 95239031031488305797872299157703352707428995576790056682263946554202201923867 | None | ||
| chip_sw_csrng_edn_concurrency | 44340928827086311099022846995504945595656910385377452798930426236978824951032 | None | ||
| chip_tl_errors | 6207995468888636716500462159953600515554531068474402797670664404851690645528 | None | ||
| chip_padctrl_attributes | 15708268344296236301894428446242854875470959057615467322284783597927619085608 | None | ||
| xbar_smoke | 21031734606681284640887418900024186753229166048000734992151332868958889634155 | None | ||
| xbar_smoke_zero_delays | 76209484075376938162139501886506734335017241715088097937396193912996615686966 | None | ||
| xbar_smoke_large_delays | 65920478199962167768223124922512673235058054088289993935831147111709374730460 | None | ||
| xbar_smoke_slow_rsp | 39331731989753249988818301225144417678625823414006143072986365858449594218497 | None | ||
| xbar_random | 55070595950131495671510585100684869334382072229276383895461098404927368043150 | None | ||
| xbar_random_zero_delays | 58990090055585423835018539303486714113089525328152587186195578831660544273896 | None | ||
| xbar_random_large_delays | 7056782906729964625497676937015025514984006481316498173971955713288871931710 | None | ||
| xbar_random_slow_rsp | 61692090300347549714506568491895495465035564096262261966638391503300731454883 | None | ||
| xbar_access_same_device | 15703246729040503810089219031720479917951830672762815514306871867005631256169 | None | ||
| xbar_access_same_device_slow_rsp | 114253484841768927699812423654075731028912255059208753428959155283322050914464 | None | ||
| xbar_same_source | 60799668002905893109626658642437025783850534273515529604879185778613521197506 | None | ||
| xbar_error_random | 72716635284374925167797339363040018808647790613726072462932398269986793746822 | None | ||
| xbar_unmapped_addr | 65834427172371265637000760399319141273009269194601764233667911114796769034361 | None | ||
| xbar_error_and_unmapped_addr | 75410865444115742406291786660807619942105078874067573529720870341734955558548 | None | ||
| xbar_stress_all | 4332179513782061442983326949711760552333114696720095499625204375614216368156 | None | ||
| xbar_stress_all_with_rand_reset | 31877405384863004057551542947088444901088578528912656808919668317739179557414 | None | ||
| xbar_stress_all_with_error | 31050425454010064862370078967995605917078960692577193373288023305658141633478 | None | ||
| xbar_stress_all_with_reset_error | 2665363241515698161725260123236823266658327874717633980416312975629487832133 | None | ||
| chip_sw_all_escalation_resets | 10318986701544537664519569522974673776015743796120555206583043993583836357511 | None | ||
| chip_sw_uart_rand_baudrate | 42251598926862668892610930117193152115387823773901615492179342977719359837170 | None | ||
| chip_sw_lc_ctrl_transition | 37980480274245047263784431540232895214619290813187536669064964789132641743591 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 63448866210030678695858338175833217576309900833491308529172696771193074615301 | None | ||
| chip_sw_csrng_edn_concurrency | 68325627824420709918951531167492374324596286413085169847323297094001068146261 | None | ||
| chip_tl_errors | 59771421494773382785905711367166217650248685056258556989122390269119865780070 | None | ||
| chip_padctrl_attributes | 93945426429882185699736558514109322279399730872989966927939795340242572747406 | None | ||
| xbar_smoke | 87871853278447439319204988411399713775297595039939255575913485074209405863147 | None | ||
| xbar_smoke_zero_delays | 16840949330711807642332241431941916234860483614767846547123170618786826847557 | None | ||
| xbar_smoke_large_delays | 94114624346055991031223088386950685183885421161693195125008631262471040964310 | None | ||
| xbar_smoke_slow_rsp | 104020451948377275995838102027327719551636697705427592000397530815499342475113 | None | ||
| xbar_random | 59771567490248171924266878662542765625934151493279252280487763551769648653637 | None | ||
| xbar_random_zero_delays | 19567327512286897854255908274819404869333938685330117292944054183678109420956 | None | ||
| xbar_random_large_delays | 59980408809624061076272125099715736436298291552220286526080447807807876198133 | None | ||
| xbar_random_slow_rsp | 84058043006072944995474481752201366513448981718880742275710900393379203323885 | None | ||
| xbar_access_same_device | 56238464833010489289997458265683794253263742296272525164631902705310397933618 | None | ||
| xbar_access_same_device_slow_rsp | 15397756079874274839542791950861898504330055560014653590180638303248898550138 | None | ||
| xbar_same_source | 72393752955544497623860497146333057332164524222032470710604813469631542023454 | None | ||
| xbar_error_random | 98262756755931304903825320166168166158023822422465450835532732603444817742345 | None | ||
| xbar_unmapped_addr | 6563492168312783751291866591614780852643035542536862321799940758742665610295 | None | ||
| xbar_error_and_unmapped_addr | 41350082548146519012615196284275030119983865165827789274739348994614303221504 | None | ||
| xbar_stress_all | 74384364431665154450119187823835061086864814152906953596900607747088860321418 | None | ||
| xbar_stress_all_with_rand_reset | 100031641728927886688642701888661566232493974980713547896246955818348127305601 | None | ||
| xbar_stress_all_with_error | 38570180458032623621807990495961329647240907158104423771433066850280671510950 | None | ||
| xbar_stress_all_with_reset_error | 72991677794649788354624139336233615359819951557331682747000823717367230035517 | None | ||
| chip_sw_all_escalation_resets | 53275395435394493825582231520998339585570482801747366399879209259352662840805 | None | ||
| chip_sw_uart_rand_baudrate | 112613654445918233271198496671923416087697843857094670697372864247999201191646 | None | ||
| chip_sw_lc_ctrl_transition | 52808894659467996217328647642696527000912698452847854782491065859841377177901 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 101277619707777979408667366348979398856251860361754050998419967218457575264925 | None | ||
| chip_tl_errors | 77826742367012807666778225050431963101597169510484093421995145789001779161344 | None | ||
| xbar_smoke | 113626110393589223249042037996462688377693199328605346908127768909114967447732 | None | ||
| xbar_smoke_zero_delays | 78356980001338217083064545661368810555202257051522315008678545405004758800486 | None | ||
| xbar_smoke_large_delays | 48887042864484666076441977310810600995888896282312242260172852696177801910618 | None | ||
| xbar_smoke_slow_rsp | 30616549208593104973937085193100347101642344912665625241469574672143506669530 | None | ||
| xbar_random | 92551915113116131046046074230444166761258423493041124690520894735926846603219 | None | ||
| xbar_random_zero_delays | 56030042250399899224517489711267935041288418524000358395789868926890437158679 | None | ||
| xbar_random_large_delays | 87622897278416002037347713439086590696721174031486693695128743129406238060617 | None | ||
| xbar_random_slow_rsp | 74220993231898306559181598162529887506749741845963872567857286255325933275321 | None | ||
| xbar_access_same_device | 15173305319905434120729255405692459278802005258126417314476318188255656333102 | None | ||
| xbar_access_same_device_slow_rsp | 43983042794918440113000107283549524350094923841211404699210086936935765488772 | None | ||
| xbar_same_source | 5215329127949729333694216132315583945098348613912659718080659426192806371952 | None | ||
| xbar_error_random | 97058823969966070422509284333782925285233147895381639397986987429289278234263 | None | ||
| xbar_unmapped_addr | 76774297822482859783147491605110389646334345442509637614393923811288119368857 | None | ||
| xbar_error_and_unmapped_addr | 1524547777857087874047943217387699901487714101556847085786946077581021907764 | None | ||
| xbar_stress_all | 89499315587607504544102456846016774641666632854651357059265866113800120626011 | None | ||
| xbar_stress_all_with_rand_reset | 8494907989920854215089703779596620430851812343938167001046341445230813659483 | None | ||
| xbar_stress_all_with_error | 74453450159605703506463785378886913932706375724873485742844093285994339671747 | None | ||
| xbar_stress_all_with_reset_error | 4859993630139563461597097968163111268590547858343345138528981083098950851507 | None | ||
| chip_sw_all_escalation_resets | 31169457692800202366712406965407359891299745598895399438423457435011594709224 | None | ||
| chip_sw_uart_rand_baudrate | 95426683055300682035954677359958897804382062950317849670650719168101194963819 | None | ||
| chip_sw_lc_ctrl_transition | 74144239673455526402070379490386546508644741959986679435705675036356247981291 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 102028503660465889993839577718064649259166287892708104427507787254043540025917 | None | ||
| chip_tl_errors | 29485376210707846253774054519186242481734767922311831328390060115351317418042 | None | ||
| xbar_smoke | 1942191095388295882751482607352864737273591501657410240223470537040151135123 | None | ||
| xbar_smoke_zero_delays | 7171384165055725258272523316580843990924365275414197861234314880352393415916 | None | ||
| xbar_smoke_large_delays | 89900574507997406737471277236620403491779013883954781987795879169271487860700 | None | ||
| xbar_smoke_slow_rsp | 18262462175435793104500656549600462480856827688562442005329405446687702068011 | None | ||
| xbar_random | 16828071541027948985828200136862787888334053101563895983098859663353303772537 | None | ||
| xbar_random_zero_delays | 297059705964550398435229813776447303454764856240913719003676020960680374812 | None | ||
| xbar_random_large_delays | 61364315758399269766646758160510221163608677720064672980474177278490788620259 | None | ||
| xbar_random_slow_rsp | 85148075480032210702950658305652529088776468372709461417012888103481518784602 | None | ||
| xbar_access_same_device | 67502916645517824042627848698867491757832209520119289977064189172767529708205 | None | ||
| xbar_access_same_device_slow_rsp | 14153046786364264193827741625805198984818831326027358905477510191737517470299 | None | ||
| xbar_same_source | 77059533937807633023077987404043824649922345916527912578711952713808279562313 | None | ||
| xbar_error_random | 67828886059554501721851000451730421053737680007203233430159657253628122053963 | None | ||
| xbar_unmapped_addr | 68743191144403799538153701048387435677538117237580825986608077717861177641347 | None | ||
| xbar_error_and_unmapped_addr | 23229101337175329427006080510847130959937895362695950515327840748617741859147 | None | ||
| xbar_stress_all | 107867650837273074497294243314828072923827124358756426959663493908509166644582 | None | ||
| xbar_stress_all_with_rand_reset | 89691515884242969914489595293933078068354201664563319817074373712971054669499 | None | ||
| xbar_stress_all_with_error | 8846271474440112746024029160325164005194624588485937786530377363992438590139 | None | ||
| xbar_stress_all_with_reset_error | 38591043728461848761026083730588105559127342371626850939031647953691113552794 | None | ||
| chip_sw_all_escalation_resets | 44190694137170263687677282752135543825858101681734570192506273808763385630428 | None | ||
| chip_sw_uart_rand_baudrate | 75732944954146077972498774972317182600643587764314835188866216911503617663011 | None | ||
| chip_sw_lc_ctrl_transition | 68194874716736661608499777080006957682045231816163427577270824714844080004291 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 105495680714610173054519870734865663504631964035774511835945726726384456615150 | None | ||
| chip_tl_errors | 43571019471218479968833858483029562244217783938380154095133522102321429882678 | None | ||
| xbar_smoke | 71419098032639872019531660461751808563229341233918838231130018716816128787143 | None | ||
| xbar_smoke_zero_delays | 81013810062751672433831347620583056996096541682548659550893810471110900179760 | None | ||
| xbar_smoke_large_delays | 108942992542465166140816006496510500821874136491696870733811866663913873329179 | None | ||
| xbar_smoke_slow_rsp | 48579501560658536188313243059181321393326336978359392886027448260201885285867 | None | ||
| xbar_random | 35075758340114029850707401161422212759299312689328497859897508454918679204336 | None | ||
| xbar_random_zero_delays | 68507410930265634780191173176283327107385714713201214033291649375445750101064 | None | ||
| xbar_random_large_delays | 24920659116264929320039816013048964319583308675377609189231799530094870644046 | None | ||
| xbar_random_slow_rsp | 65972634750712167696422107810599989314682465963532632063363054584037690749742 | None | ||
| xbar_access_same_device | 69933774697451190177118695879238633483623840921678544692145065415547066447722 | None | ||
| xbar_access_same_device_slow_rsp | 109715870961305330260350481985727408633933569763333715396198547949638038135673 | None | ||
| xbar_same_source | 93374001333907559388675621857957720545232225565136492738272733463371766783059 | None | ||
| xbar_error_random | 42865512365962166338529183437674520156513131850189611290493085541374743154498 | None | ||
| xbar_unmapped_addr | 26223028301584720398079332410130868701260354754615568478724093887863651075986 | None | ||
| xbar_error_and_unmapped_addr | 70980561639215267301615006899429898003534105816279717893934402866969389838278 | None | ||
| xbar_stress_all | 61652371260674832531432569161798351116760951948577889114545536307968290973831 | None | ||
| xbar_stress_all_with_rand_reset | 46864564879926159158023311211688809762810948699415221888069799172116158091841 | None | ||
| xbar_stress_all_with_error | 87280676627374972462843403842059547633899222034471664880906725782322275357113 | None | ||
| xbar_stress_all_with_reset_error | 95471238369987240988077174740020095342638723003601973198765105589739450457244 | None | ||
| chip_sw_all_escalation_resets | 18335688363233468019896705916991284999674005040232477100027753287770661168553 | None | ||
| chip_sw_uart_rand_baudrate | 35668012802648701198925062950907975635975137479755289608923274776320778386225 | None | ||
| chip_sw_lc_ctrl_transition | 4499715144705713807171765157246976042526357928009986307626924692766664311228 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 34814531751193330410515733727073209073111764193524468088515176584650424953847 | None | ||
| chip_tl_errors | 18818704219358011071015110355341569064527123901727994787290780575043222593064 | None | ||
| xbar_smoke | 18543753256027660850401195943221615583027174877667185338844777829554137023028 | None | ||
| xbar_smoke_zero_delays | 15510867640238779499036830263361459658022961105695579915996033818131477835222 | None | ||
| xbar_smoke_large_delays | 39596344990018345655724991189973904707457116057586719321446525626122771929607 | None | ||
| xbar_smoke_slow_rsp | 50761345810102846750001963009457660221821615257307151006955597488493990701657 | None | ||
| xbar_random | 43943668454132622530753319056174378897605717522608766101256944585576704278855 | None | ||
| xbar_random_zero_delays | 64731596210054711933452192522620405179816300141201324073642219056087714238796 | None | ||
| xbar_random_large_delays | 109459787322523284720130371296183726994678951400153044665810399742446916319 | None | ||
| xbar_random_slow_rsp | 89028125536586019185238693753921060677479892294394652320409213751761993125711 | None | ||
| xbar_access_same_device | 109824893473623328783185118695594892448847162617288273268988203203997695896964 | None | ||
| xbar_access_same_device_slow_rsp | 22669960101013211657512837116874596152582265609086299787187338103168517956650 | None | ||
| xbar_same_source | 75862938153512174956218081688474097595267453668233186311999309033846943604342 | None | ||
| xbar_error_random | 27644217993043953417926807286837912721917594157977970132414496235864372278374 | None | ||
| xbar_unmapped_addr | 50468433329657644879568489920373313434653326711936352430731180598559110353114 | None | ||
| xbar_error_and_unmapped_addr | 49923057376706855498203557138078525978415431347488992979732154307398745350922 | None | ||
| xbar_stress_all | 2784912984035136673922226868418880284353614989171964049159949101195087590012 | None | ||
| xbar_stress_all_with_rand_reset | 25119001215070846538841998357152644990494476175322704955774384459068091514682 | None | ||
| xbar_stress_all_with_error | 14276601865222472127814289428524513420722731490071711520547305453299759902771 | None | ||
| xbar_stress_all_with_reset_error | 3173959035910107543656736010556192362837407049606249455762060098413029894008 | None | ||
| chip_sw_all_escalation_resets | 97758011901761105375871981011924488545314404712318518502575026638247259153963 | None | ||
| chip_sw_uart_rand_baudrate | 97079049289372541622751742934108137000491659633884874828268583057461661048100 | None | ||
| chip_sw_lc_ctrl_transition | 35319074072904080118296213529768486955552737310947735974494234309247293294254 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 9494006551319666115351031172326817627888604412677847188012974409465260250809 | None | ||
| chip_tl_errors | 41272182509293952375410560420669260526189143428673012726995425456833665370641 | None | ||
| xbar_smoke | 89398384112173335393405913409184041312220523788446525388217955549079941350804 | None | ||
| xbar_smoke_zero_delays | 75624855932762934645582338070537129538793230473119932136417177663692219361007 | None | ||
| xbar_smoke_large_delays | 84264250633328069967795082468222208038586956505655907585582832868464418269043 | None | ||
| xbar_smoke_slow_rsp | 49148460901558925676750655215106779014153062106215583313650903784524554565211 | None | ||
| xbar_random | 35103809975526938681430449385352786194299937362891878536953764064438883518171 | None | ||
| xbar_random_zero_delays | 42104612390543983258109810158069299561031333144076409165668450347699420762724 | None | ||
| xbar_random_large_delays | 8551086820656196180086242327197217274691609978466366708481990430620973707460 | None | ||
| xbar_random_slow_rsp | 18062936571558424795921907167005190480406787656094732219020239780862035492918 | None | ||
| xbar_access_same_device | 76236421634933875277031979826531148446171190991210169224842843670669009415117 | None | ||
| xbar_access_same_device_slow_rsp | 26835849092576821747579532696381127517199156469379083808697740097323409834064 | None | ||
| xbar_same_source | 84800097337100639245488785158170387524162180126109704616444335003650277163058 | None | ||
| xbar_error_random | 12598916656578409382584858078137822052546995870654154759922425132349985701460 | None | ||
| xbar_unmapped_addr | 30742555377495978744853491364122812436968376970798839183123924785153646941944 | None | ||
| xbar_error_and_unmapped_addr | 102412799954842821289451602066013167545410728209698382914721640938333804269826 | None | ||
| xbar_stress_all | 20652781523041420810137465245543569012968114898784363018876442666127035520119 | None | ||
| xbar_stress_all_with_rand_reset | 229165399957618398536580819504572570109832664765957329350161407099039765394 | None | ||
| xbar_stress_all_with_error | 82930488421809896210517348120441575330979926678075823095457398680392546978553 | None | ||
| xbar_stress_all_with_reset_error | 81826815273485258777313532672128584536713792575352558208941172603063207879018 | None | ||
| chip_sw_all_escalation_resets | 43068147849219326334473819210044575802606594332955631026323769528515227564003 | None | ||
| chip_sw_uart_rand_baudrate | 27858734696093083280419008456418495125669889917753219481542520319710709291169 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 97505322048100334063192784863809377654550208585987975359335404407445431512222 | None | ||
| chip_tl_errors | 21823693224351658982012090217569805199986186649907814670798622966311214074747 | None | ||
| xbar_smoke | 91055551743819169985168533320496624089929605842763405481399997099169566101933 | None | ||
| xbar_smoke_zero_delays | 92331265784949993062477645626447744479751383651054356561032359274147259589190 | None | ||
| xbar_smoke_large_delays | 41050830849888688403103669401237107015740904388613974067815112872889296073786 | None | ||
| xbar_smoke_slow_rsp | 4792241457192278850440574182586989781611585337240043055691682084477633871032 | None | ||
| xbar_random | 67419355631046173912356910326013780362992061445273879658174914355241087743724 | None | ||
| xbar_random_zero_delays | 7999835491229597525397968088322199842216379634250107905270419792517364949267 | None | ||
| xbar_random_large_delays | 28044083896550706031746908042801018214736040991639765691365406372133058659123 | None | ||
| xbar_random_slow_rsp | 24292839336796850817351381350400639661505353250670457825596338782529046495383 | None | ||
| xbar_access_same_device | 31467788807834424768055637605074384834355766194453279594536997730674245593185 | None | ||
| xbar_access_same_device_slow_rsp | 182217031177012205101139499919121461700705589088856044659993583258751668271 | None | ||
| xbar_same_source | 106281386820520596069684939999756622701121852470945151752265971028054447375041 | None | ||
| xbar_error_random | 110860386776072415569906551574112655627468675678215249203549089388730445941846 | None | ||
| xbar_unmapped_addr | 39997009188086125240362681437909139992268924071803680397651810340891826969954 | None | ||
| xbar_error_and_unmapped_addr | 2570910595451700123154893493906310358348129590852393630966760305442898801585 | None | ||
| xbar_stress_all | 67861371855950044920358672311860834465618732897883381170234587047690346923243 | None | ||
| xbar_stress_all_with_rand_reset | 95569239705954181538065176572781194398671159025739301376235998163986261343463 | None | ||
| xbar_stress_all_with_error | 109724988413328223312186675192334747099633133069997083240915754804013014754823 | None | ||
| xbar_stress_all_with_reset_error | 50619955401556964148246947908148698312693641390320251909232216665195812319449 | None | ||
| chip_sw_all_escalation_resets | 101429740326053696192324718716151805541797853818857212689758269791072814515767 | None | ||
| chip_sw_uart_rand_baudrate | 104173645513151759007944687867728849409000191166446135015505739688947142559317 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 13457160080093930077615478397675814917980015264343920914563056905671098213494 | None | ||
| chip_tl_errors | 15815356056643135496345305853904048300544642668211964625028845943312504293833 | None | ||
| xbar_smoke | 114287650200630962624229971879076987858109388252699724432708792131546931375815 | None | ||
| xbar_smoke_zero_delays | 52703555732602315726564837652672217374860842603208385004024683963160305262623 | None | ||
| xbar_smoke_large_delays | 24409372773567687677137942759261970737890399985220483462785136575001489348950 | None | ||
| xbar_smoke_slow_rsp | 16509706164950972926646464207972371782651724420250917059281612388240018353906 | None | ||
| xbar_random | 61429260258024258612950303340417126459138250281036165637163243087670274359734 | None | ||
| xbar_random_zero_delays | 18675938429068076353826855698189542464271356046559623140683393978344903295067 | None | ||
| xbar_random_large_delays | 24938979536862913158394558720195347944710893580352426599615228731088970415295 | None | ||
| xbar_random_slow_rsp | 44565829199130572665852153075598343656461140485688684076862848641450387438845 | None | ||
| xbar_access_same_device | 48135753284007242465968116132282181288869689484400689860803361754156912118254 | None | ||
| xbar_access_same_device_slow_rsp | 52527539094659307086486510130633258878422968039390600496817223272877509714418 | None | ||
| xbar_same_source | 102906243354243947724350656853944720406180391649499690731764750632724508184458 | None | ||
| xbar_error_random | 66455231185550641806663813953601249045531752044128098271813647693731760568496 | None | ||
| xbar_unmapped_addr | 8519087416147435807032667639396247391764732010989813516064970642754658837195 | None | ||
| xbar_error_and_unmapped_addr | 51901234592822483920360493280678147151150664184247803266267692121355512512071 | None | ||
| xbar_stress_all | 12728814613992471166097571906581157465544915073211476592696826032337555152658 | None | ||
| xbar_stress_all_with_rand_reset | 57978302980014701095726636177481706784248364817822684159951359896736694088918 | None | ||
| xbar_stress_all_with_error | 31491781112368830174278399615683866613366901123167314570638610807714807361896 | None | ||
| xbar_stress_all_with_reset_error | 103470603344815066514879662412604446601208328366759585674828105799067419470249 | None | ||
| chip_sw_all_escalation_resets | 68981236621694831271664211936007767022927424914405510777205962647255749188204 | None | ||
| chip_sw_uart_rand_baudrate | 108601199288375687905394647478510824325868634133913986891579033211816509071660 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 102977089673031294485708966978176898187324972286211644811318328352555142883385 | None | ||
| chip_tl_errors | 67966721670297725328337278356321968872550440771282282324743437294226638818561 | None | ||
| xbar_smoke | 4287114945576305203068408401886329579127123197654245454079641913579183972534 | None | ||
| xbar_smoke_zero_delays | 58355582848188858496723205738346495225943917337819134670728193329460303766526 | None | ||
| xbar_smoke_large_delays | 114100060230265179772071495321883206604939785967277191653496349700381625724534 | None | ||
| xbar_smoke_slow_rsp | 18476796362391992546115324914612056533916192617474487501355417170396684294354 | None | ||
| xbar_random | 73308113408582640668141324713044513387217614898594590430015510791935066060916 | None | ||
| xbar_random_zero_delays | 97593146665962613608157589060740948834569699240859524454633681654382171770566 | None | ||
| xbar_random_large_delays | 35503629029314281171455570351432550200909207150743861185358208801808808396191 | None | ||
| xbar_random_slow_rsp | 7084351770427845743244623781579461733696620383006729457129468126199823152099 | None | ||
| xbar_access_same_device | 64045769084262166861606569948704926482876428773733640980330884703426249224242 | None | ||
| xbar_access_same_device_slow_rsp | 39857425811639428410183581361550499514673836386926094630504013003601074956739 | None | ||
| xbar_same_source | 49682417901920866970901042541981788177560007979365508255818092257199032171432 | None | ||
| xbar_error_random | 57987720320199176271016507047067066775304099678722286296622586736466513526041 | None | ||
| xbar_unmapped_addr | 60758542221781354663999331413162800340931010836998961580797517704371516470586 | None | ||
| xbar_error_and_unmapped_addr | 109023400747567310402068449535444351742848472496375480294575418318341676420757 | None | ||
| xbar_stress_all | 36780273092066936028801111381915505943052229001883142035668912931664131674353 | None | ||
| xbar_stress_all_with_rand_reset | 33681282641740528086116363746090821556403680467667881425106125558386688869754 | None | ||
| xbar_stress_all_with_error | 41017323360563272967965238877079865447873398542044730175080580016499758753929 | None | ||
| xbar_stress_all_with_reset_error | 20452474176673646362799637319606050613135595410290130081102818603350851241056 | None | ||
| chip_sw_all_escalation_resets | 10532714942119076232632534156021400988963630519305034706724192089078956531149 | None | ||
| chip_sw_uart_rand_baudrate | 26372517551751728599530147150087614117955941533763792384514656416988674697794 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 100540185238990909505400895415390708643286557157903461649067046012621548779582 | None | ||
| chip_tl_errors | 97126459270384757214737093199466341204984383666539333886179088955203311680548 | None | ||
| xbar_smoke | 41183280481743516417844413346914686938685509440580962540242170065325603210501 | None | ||
| xbar_smoke_zero_delays | 917186467088525788372147697568735763485023740220633906162479530034165063759 | None | ||
| xbar_smoke_large_delays | 9988732975223670483711473055723403691100781238903231092806952591833203800517 | None | ||
| xbar_smoke_slow_rsp | 26341671226281932676388384105775120700948128402647832281905286853948346587060 | None | ||
| xbar_random | 74654742001405526330106683344297558668428061673382414161840837318779400173292 | None | ||
| xbar_random_zero_delays | 44138971738922395422668309253576337962107846209996467571922129973777801452731 | None | ||
| xbar_random_large_delays | 65236296422153720095625078095669004673530626386804871251560837421872858536976 | None | ||
| xbar_random_slow_rsp | 78883302000552700396873129345135559378165127553456468369051159045133725027176 | None | ||
| xbar_access_same_device | 80344090591508235321367135762188140622121995638904389363479004696300440993657 | None | ||
| xbar_access_same_device_slow_rsp | 96406696602966345726571715729484758184647572866613380822247697255975435559279 | None | ||
| xbar_same_source | 97005608057259927073681025527863734619406881268262387867816325170686433012269 | None | ||
| xbar_error_random | 101742229445112594037216348673026026012047798995995726935273869486621175544818 | None | ||
| xbar_unmapped_addr | 58307236829516099498639897206214673556632822502050099191376396066910941909721 | None | ||
| xbar_error_and_unmapped_addr | 85849299814957437527632987601158790352655353752127717133073358477861426250062 | None | ||
| xbar_stress_all | 104578104995712995651057363125667705476972978936042453646804433935025610518523 | None | ||
| xbar_stress_all_with_rand_reset | 44152645808755016679807432360869727408029793104856152988375278438617525236561 | None | ||
| xbar_stress_all_with_error | 52725127457935364347107201731307589657965278083012493874814321642708774889307 | None | ||
| xbar_stress_all_with_reset_error | 32955919581198048079303020999431181315423123279774377562243526147077648593264 | None | ||
| chip_sw_all_escalation_resets | 65901577585050490464563763586344221447761734719725799339018970267969703119163 | None | ||
| chip_sw_uart_rand_baudrate | 29231007085900485379239459628919988291941033923687410971951716650878781790518 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 37511035094188863494663227148125284445053444992739845277701912560141889210383 | None | ||
| chip_tl_errors | 31367501663216198937064284211584244160366898418199807548175083091045236288149 | None | ||
| xbar_smoke | 92659586328239991504540743050440453575721367085921874435930395745860327542346 | None | ||
| xbar_smoke_zero_delays | 31420201103612929541323889667494298988615001221439401832083401052973752574152 | None | ||
| xbar_smoke_large_delays | 65311483693788518155227142657892505677316038330069152323076745454873167599536 | None | ||
| xbar_smoke_slow_rsp | 24050395318867461218088574785054044895816421947925739362068064671379390045295 | None | ||
| xbar_random | 101201472737464369705663453524963853651732796319547194511954010968785045130555 | None | ||
| xbar_random_zero_delays | 47554966338832357616333502394524956527391242759628025764119879478752536849028 | None | ||
| xbar_random_large_delays | 67861452425090374305830678695927100215241815698138388186162024099991573667345 | None | ||
| xbar_random_slow_rsp | 114146290747655532749737583074854792149030423758609561169185617878378327622003 | None | ||
| xbar_access_same_device | 107569970019861231345413518132232647038808410666221575094724077076153234625878 | None | ||
| xbar_access_same_device_slow_rsp | 15564323406540602710533412755744902711335261048037553685786873651209722440665 | None | ||
| xbar_same_source | 107849537043702597670093753151405680571480160077208147343398758300382903667422 | None | ||
| xbar_error_random | 30736634549316079657961621873106312975045503320129024247378511734341133188301 | None | ||
| xbar_unmapped_addr | 18537019377307537804529974735502773215530666364991742814843817119686254859753 | None | ||
| xbar_error_and_unmapped_addr | 106796283264287728794027081039935869637206057591622956510721939947137657922649 | None | ||
| xbar_stress_all | 49938045665093438155927418531866355530727970796585667096917027548817677178651 | None | ||
| xbar_stress_all_with_rand_reset | 92587657870336326949964506579510439952120472005829368501203745202979424638379 | None | ||
| xbar_stress_all_with_error | 114337482610686954774499410358031098888116550751483574968957170896949078491908 | None | ||
| xbar_stress_all_with_reset_error | 84691411043553562980987307301999582484303349098754956959941756723465900223829 | None | ||
| chip_sw_all_escalation_resets | 44649862394025816186243002361517046355767926632518683891776633221563054957287 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 4307710405009635670672238810713614464069300697281270088613643411666825917504 | None | ||
| chip_tl_errors | 52697013602057795391421101073751554692865218149583041639431460997526783316827 | None | ||
| xbar_smoke | 72824346287470545257591702852223106366579002341660657156914442778722323908974 | None | ||
| xbar_smoke_zero_delays | 68000510344237152823379645927697382511184280513896542471251492620549080887823 | None | ||
| xbar_smoke_large_delays | 96132556675525932452046837332020836548207826320954179817873287193528987387736 | None | ||
| xbar_smoke_slow_rsp | 48625017311551611061586434513383796531305746570614716474425939542946299652343 | None | ||
| xbar_random | 86839484464168294497144024782199674241669529612481845716610790975674160400964 | None | ||
| xbar_random_zero_delays | 94691119257787054021752096242791863522208908652821998247067168338724461489042 | None | ||
| xbar_random_large_delays | 110927121357726416597092203862046791630321180335992585417354593532147136995237 | None | ||
| xbar_random_slow_rsp | 105983608406363383965200712586422601497981337650478070275446305031635710040082 | None | ||
| xbar_access_same_device | 45091676608788517865862963843988989292083663860072666158377762668997047180090 | None | ||
| xbar_access_same_device_slow_rsp | 59653356749114088745778041599895500643294155254588398858971153180919567382994 | None | ||
| xbar_same_source | 40400004364907558068640011105834873639763998722191520484553532964370121347356 | None | ||
| xbar_error_random | 10858349706187532499372582213349657896902675092105882561875789518587295745852 | None | ||
| xbar_unmapped_addr | 29462016646041612994720917151470382818290979824822740008633311705219962186987 | None | ||
| xbar_error_and_unmapped_addr | 21577153073865398703785696425106186165206183081980926520540086351462896932624 | None | ||
| xbar_stress_all | 90759660973471776571227816706159282181909441561463645900448057717933995966837 | None | ||
| xbar_stress_all_with_rand_reset | 42472278426338497861310926234027367752902844481403413303352440481907744073023 | None | ||
| xbar_stress_all_with_error | 104857092956119484647988715060251110961391127565251120495951051086941749460210 | None | ||
| xbar_stress_all_with_reset_error | 18901888273624528327176249428479310219253554113290789570149107071654907312665 | None | ||
| chip_sw_all_escalation_resets | 95713516866929352192840168537065936265119495082692362568016691925855448255263 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 30639559224077502645991575615311410368970032223933681318177257963836781538912 | None | ||
| chip_tl_errors | 60897476209771597744044830305751339849277001120454144183793034994765507013137 | None | ||
| xbar_smoke | 2550904053470510371326879278027173004107317633129418823700151706922611348719 | None | ||
| xbar_smoke_zero_delays | 62941467040125544236760677394377221663945884013453054894734001860038941007246 | None | ||
| xbar_smoke_large_delays | 24141829404611142297397507245295212858099495345834046173101102468539640135767 | None | ||
| xbar_smoke_slow_rsp | 36802819346287487558988303504409439281176007825906767237149572586143073502799 | None | ||
| xbar_random | 113533069104260945100700212778723376075610563050101075094246347202908987317514 | None | ||
| xbar_random_zero_delays | 52213608961497100146653417996887154782820663261831132193442347285288421557485 | None | ||
| xbar_random_large_delays | 25040266068332514724410719572887856913352299438161131423957065964023041739367 | None | ||
| xbar_random_slow_rsp | 95697004870316816452122577215827969267365994855616970593612852360296731063200 | None | ||
| xbar_access_same_device | 79755748356866101607555645684019594790632540517348632204776149067981341355378 | None | ||
| xbar_access_same_device_slow_rsp | 13850382991519027855978601901445380021512666548377504022342814786592585067261 | None | ||
| xbar_same_source | 27922547421471996234293626993507800957043159765825128329719418867438415564517 | None | ||
| xbar_error_random | 114944199612161253537982869615005312988859818454276894243077313497323516828883 | None | ||
| xbar_unmapped_addr | 40844618721842359485194309974792851243558761416218333905640031126078467740268 | None | ||
| xbar_error_and_unmapped_addr | 75239457771287723952021835679737253071602650551376460443681788292794706323898 | None | ||
| xbar_stress_all | 112591846705918562508693033326841442380562526727371899278662391047081870475320 | None | ||
| xbar_stress_all_with_rand_reset | 9348083533864967304564583007029406385477921839862857726292421371430702364424 | None | ||
| xbar_stress_all_with_error | 14104787165777250787393893508942566096513038903823433303771104878061470860564 | None | ||
| xbar_stress_all_with_reset_error | 41688700720298031985691755254036299633637269018052517366056406118136770440455 | None | ||
| chip_sw_all_escalation_resets | 50321086527788036836283136111484508203044289801928337043291137201311520323317 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 6405729947669229532388991140685069607136797614062302492536508067685598566193 | None | ||
| chip_tl_errors | 50929131208749289125091576411861774530760590008559082823940226504013594091712 | None | ||
| xbar_smoke | 112543129880739169709680206982908680714811725877950275698130811865719514928015 | None | ||
| xbar_smoke_zero_delays | 103391753641621805511602329944974240099722077123747590776341423594575380801896 | None | ||
| xbar_smoke_large_delays | 20926389823301329119002566617553720380559929703769213579818751387935766373787 | None | ||
| xbar_smoke_slow_rsp | 36357715771234004639160070684551627350194859462564426161813664683331434717779 | None | ||
| xbar_random | 8308247913186490873577027400802532558784486609246664088872028874956368622920 | None | ||
| xbar_random_zero_delays | 74153046515973230190360141795167496910995389140878485660945000789523194497915 | None | ||
| xbar_random_large_delays | 95878796533795589680661633663340263370030877954462083720459456397336927029564 | None | ||
| xbar_random_slow_rsp | 72045551987405753698336406858047800523916973816873145158381698799459870641592 | None | ||
| xbar_access_same_device | 104451486778951695253534698444981317012306293810512739819179182021401754356791 | None | ||
| xbar_access_same_device_slow_rsp | 25842644927655949341739862914329917316467831445455252336646347527278235350064 | None | ||
| xbar_same_source | 87488476696349861604370707761338855538982207691183982744258466481500424235233 | None | ||
| xbar_error_random | 7929880893829684030469357760673427397479526383912393127755778076762258630305 | None | ||
| xbar_unmapped_addr | 108818543807676409328784940646982418509830550544193319128841168943332088914278 | None | ||
| xbar_error_and_unmapped_addr | 50779710392026207283148133584567485115060457432389301468910325982515318297285 | None | ||
| xbar_stress_all | 37004923641223345341777572572145747078597485970010672405536263223895814565727 | None | ||
| xbar_stress_all_with_rand_reset | 30180017034844310870767740732005395054208950218213827069680379272297761515178 | None | ||
| xbar_stress_all_with_error | 114452178730327290315084028008119285903023282611858063181781061212261026272329 | None | ||
| xbar_stress_all_with_reset_error | 17284454888374631942361305997050988004664656252731019511104249838370039223256 | None | ||
| chip_sw_all_escalation_resets | 87134072278934932139830153041016567785624124484902740463020987209235833236051 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 114449494611911459035393762513035675414433290115958604153816218673960103705841 | None | ||
| chip_tl_errors | 1833767391216325420856102699673135718784279343904435594193801334745409569537 | None | ||
| xbar_smoke | 96728838647414662103753504482283798426181499360537325087788870607469659717694 | None | ||
| xbar_smoke_zero_delays | 115453952970826432006994994958515228864118586919366428136478387530019146379721 | None | ||
| xbar_smoke_large_delays | 68541617022335418405043862527297437642431535681961387312125057989514640012932 | None | ||
| xbar_smoke_slow_rsp | 110849720995312793523543673131132697029637776316631677800843345504999265078082 | None | ||
| xbar_random | 68137769565130520907008417217099945515938486523001335984664050499097928000224 | None | ||
| xbar_random_zero_delays | 70011626202354435138853127068429642104755678291042541754572674954221954414783 | None | ||
| xbar_random_large_delays | 83434869634480150473016570419998869701376242527439584859733281426852942221537 | None | ||
| xbar_random_slow_rsp | 61853764799848127789136933622817165099460215759428922435129428975829073568540 | None | ||
| xbar_access_same_device | 518523344387254615301265273643437609290923978914423350467602663729073139160 | None | ||
| xbar_access_same_device_slow_rsp | 3352385084095381295924197239812792467864391468281781284894767261155492793229 | None | ||
| xbar_same_source | 96331849721688026876934445053992478579884675050774975973646753508594213830906 | None | ||
| xbar_error_random | 97371780349208086590622740723100352762504958479579292215804143158486777471481 | None | ||
| xbar_unmapped_addr | 107677409855304937699492477928599009355065852250893183425754064561755642361718 | None | ||
| xbar_error_and_unmapped_addr | 18612525255364772471847173346593901182752932105181178077121103844111503073652 | None | ||
| xbar_stress_all | 82918334274874424246686367421497040911164830913207792033347571872571973200394 | None | ||
| xbar_stress_all_with_rand_reset | 28217675357175415071337279140914713859401209253311553178413937001563403110755 | None | ||
| xbar_stress_all_with_error | 110801329166369465272105467329060989441618857327763664515807954174598246561108 | None | ||
| xbar_stress_all_with_reset_error | 101492508639659525264992873424530701118321675869478358799900855511334395856044 | None | ||
| chip_sw_all_escalation_resets | 76473988832781773719914201592376882511629738438594095125159041291740514089892 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 13627950158943514061850253458500672991593447209547687689192502936417782008435 | None | ||
| chip_tl_errors | 19682100419592114064221761869307617307692473665614734537997603890839753080289 | None | ||
| xbar_smoke | 81533373253470455685159101495969376047940510768181692030319801475093485851363 | None | ||
| xbar_smoke_zero_delays | 57218203362338451031663708148294348921406294629153305098000572229540490729083 | None | ||
| xbar_smoke_large_delays | 94217758374990674587946623785032037356829840245392267062594680545185615158657 | None | ||
| xbar_smoke_slow_rsp | 107390137233529345538790628562524662677501274973142236860905078590710843155630 | None | ||
| xbar_random | 37403415483686200402260307006917709383722783884933669850077884552195223701410 | None | ||
| xbar_random_zero_delays | 115315903397794008600553570987421554256953180767455747093528452751698838146669 | None | ||
| xbar_random_large_delays | 26364393793436947391886467698372393147385567441983549370365038497566483266228 | None | ||
| xbar_random_slow_rsp | 88076864612805442282059873825957749853018863871085882528474485543069102517068 | None | ||
| xbar_access_same_device | 39959345020468249348104813180123428642949593373365491393914792615027098021891 | None | ||
| xbar_access_same_device_slow_rsp | 85653812924088352571259944024213600772332955258747906298387819210037751742307 | None | ||
| xbar_same_source | 110444461339097702408367435912353547600308928333426133881505083348973210985206 | None | ||
| xbar_error_random | 38369767673323336043140808474620892222847646324528767703987222879228482380024 | None | ||
| xbar_unmapped_addr | 99011942451731696365031294751322673233364766760304406216262705069064755301153 | None | ||
| xbar_error_and_unmapped_addr | 63571286308324060328666931178537629029418341636793680377299561923346765903587 | None | ||
| xbar_stress_all | 22790368434167861852656480438292876298819207083618891952400778893393050577437 | None | ||
| xbar_stress_all_with_rand_reset | 35568596362713672561125263507185322667545711880027726692013372113087212671940 | None | ||
| xbar_stress_all_with_error | 95968020093580411721996740068323302906882347157358027589406872102080166824823 | None | ||
| xbar_stress_all_with_reset_error | 82706666970205660104684362296236696696570761061196736578639126249113350777248 | None | ||
| chip_sw_all_escalation_resets | 104340378959050383614931096717711866317523517863161125411386005679427961084145 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 89340766295068623827894368102658742492398180641243440535864430717873308072484 | None | ||
| chip_tl_errors | 3144974168844651542669583731173084301161361052885355880110160238077476810191 | None | ||
| xbar_smoke | 11646445549420780051098361776520397595965647865700770979378411195987529284971 | None | ||
| xbar_smoke_zero_delays | 60662349182994520586456486816866645929261365616688217872624875736646524510130 | None | ||
| xbar_smoke_large_delays | 95141317569654928790601474284272277541338284477774514510822628955566885102002 | None | ||
| xbar_smoke_slow_rsp | 19469396220854394400259096493642477771593696347129087532069537170616248125215 | None | ||
| xbar_random | 36871454523370069816339583365227574442437081598257667977993588483662880117235 | None | ||
| xbar_random_zero_delays | 16196419435898416938185393274776531578718285887353371087198040175386690648251 | None | ||
| xbar_random_large_delays | 14874241428191286919237610407961275843533088217040178534636512442188425728265 | None | ||
| xbar_random_slow_rsp | 104117154630178897147614958869526160798493193638709491681526049523949236706798 | None | ||
| xbar_access_same_device | 27110925720783925035573257922073428529189385454580114675514750846584431357526 | None | ||
| xbar_access_same_device_slow_rsp | 4000094437235157594424856802203724014941325997109419850287875913067897505915 | None | ||
| xbar_same_source | 50455200964016886836891200857340401705906722073697186555790168037776264301217 | None | ||
| xbar_error_random | 54817264685220330447018798840284326780216885311327486286907497250202787013590 | None | ||
| xbar_unmapped_addr | 115104979811878435357589180609325438975876410990196779308241109889526317772382 | None | ||
| xbar_error_and_unmapped_addr | 64507850995600363529502172461449440439643663216437435285626418777007835848339 | None | ||
| xbar_stress_all | 56577223645021367649739436347176480646648333684374552005902604889082082139356 | None | ||
| xbar_stress_all_with_rand_reset | 43198518530394606062881459093591361372389034442629091805503065621770806293998 | None | ||
| xbar_stress_all_with_error | 110567032756054307450357738042185098882949443131487336734849528347356388101487 | None | ||
| xbar_stress_all_with_reset_error | 47719920774168735242518452840070318766597832532753327659061566947709108581471 | None | ||
| chip_sw_all_escalation_resets | 6038990296395343458707072101411563517913839303519544072329278980295568936448 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 110441291487681439342162705797761420651462355375429334275107239845076253397061 | None | ||
| chip_tl_errors | 58814400079167111125702982275499917953340040795165303549063828205283198122284 | None | ||
| xbar_smoke | 89348907186867050512189387654905441104166590281124312315918071578908090755061 | None | ||
| xbar_smoke_zero_delays | 55819684020293459793860114173656308524894706466614984638752049498741292101498 | None | ||
| xbar_smoke_large_delays | 69343379329407466765589989844468517511563358534009215623443707467736775338320 | None | ||
| xbar_smoke_slow_rsp | 13142526067855842959870200972324980528910002990830763331688328281684547588148 | None | ||
| xbar_random | 99911238058155308914393455995942620927260260254969677178144646924814998275320 | None | ||
| xbar_random_zero_delays | 2463978287008275219995531139284552173812140605247978843142677594889449115446 | None | ||
| xbar_random_large_delays | 78390617324735570474477623050012321484261894337439083885867463526588031443964 | None | ||
| xbar_random_slow_rsp | 111482307168729019992362969842429366215676806799133704243174673858575204447052 | None | ||
| xbar_access_same_device | 42603718572003615475479702043254739785967979258935955031827573685849076377454 | None | ||
| xbar_access_same_device_slow_rsp | 52863262491544843231958431293852797197461050632201166861670093874212927761103 | None | ||
| xbar_same_source | 100949063484149740300960165806175482334543892119103412083289200746716725390281 | None | ||
| xbar_error_random | 62794377114553378562130388971624132268219705950225979191766581132130902892069 | None | ||
| xbar_unmapped_addr | 8281075635719476692158742357351595583721529519845159947762673719072860425280 | None | ||
| xbar_error_and_unmapped_addr | 18672433340375298126016118097502643635774413259821781401995088008918797625862 | None | ||
| xbar_stress_all | 106725997544033442775747676297771319952150945586015279791234142245062286633978 | None | ||
| xbar_stress_all_with_rand_reset | 43227009201174325230587840493357292872178674319938646475576274450977225159834 | None | ||
| xbar_stress_all_with_error | 22597490531466072063132482167307594811901319440806769347966866123643007269902 | None | ||
| xbar_stress_all_with_reset_error | 76216056464402808793990162813109242236297642706761097450852461798669126011088 | None | ||
| chip_sw_all_escalation_resets | 68597074753220968342495208650101925429400398880799497260092353634532138950524 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 10586954280923476585576771384830634411070477049832072357470170758165665300394 | None | ||
| chip_tl_errors | 55183226624845605206873556329668833204424129207703486239346901253165775252053 | None | ||
| xbar_smoke | 39044692467479320099190034731398043246978767125108213882257605173011492625728 | None | ||
| xbar_smoke_zero_delays | 98589389212812182469502779830274327012630362900998892490655899371045570046596 | None | ||
| xbar_smoke_large_delays | 5334150959106699526167556143956349919983629359749297510544451576909900184690 | None | ||
| xbar_smoke_slow_rsp | 29005919745360482893507311899002061548730021483947640925180236418613157534962 | None | ||
| xbar_random | 44718116215745855972257561012461059464798972809825220299694179217481397495828 | None | ||
| xbar_random_zero_delays | 26301178393076507184890169838935730187842114395344447400788787128564392195057 | None | ||
| xbar_random_large_delays | 97244330844041127882864852823323174736485723253652990410119054758755989538928 | None | ||
| xbar_random_slow_rsp | 94487202753449612583704974137880015842990512533185986816976464733506474704947 | None | ||
| xbar_access_same_device | 27654610707138220758676528675578662719531472363546079157215535210973050936110 | None | ||
| xbar_access_same_device_slow_rsp | 86929940460041923242215976964051539028632041094481493051743444471458423617915 | None | ||
| xbar_same_source | 33335829453610083690104105136558384052471344117213586605104210509556205081280 | None | ||
| xbar_error_random | 66421657092820905171920220065204207591210114623014091593163622891438433200742 | None | ||
| xbar_unmapped_addr | 3437521132990536183362712769202707678419773995107670909694865584050490720037 | None | ||
| xbar_error_and_unmapped_addr | 88962092927544364259117429352180567678169844693421162203076031678750527014133 | None | ||
| xbar_stress_all | 83654364000398718770142664766444806406853678859907852868760347198296331589140 | None | ||
| xbar_stress_all_with_rand_reset | 111374629813966804041100408942147420671078163080465267357289015780622158264032 | None | ||
| xbar_stress_all_with_error | 3052285627177153696289653602199137421721507964931183162512934984295395119999 | None | ||
| xbar_stress_all_with_reset_error | 89883578570858780418223057329587784089364043272930943156368544370568659256924 | None | ||
| chip_sw_all_escalation_resets | 13532332145438269243213067415215399261862310820880117643051853754405997026175 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 44435617051693964205962301068163039744313657275760272786447539715351457244816 | None | ||
| chip_tl_errors | 99462470246758641035487485015514251442036595014040029448699892407648377301339 | None | ||
| xbar_smoke | 38236323875188473450360852392105596007661171475228794929197630245742609674833 | None | ||
| xbar_smoke_zero_delays | 53502197617735178803802013195312104286323163668425647325077907700601191366336 | None | ||
| xbar_smoke_large_delays | 64197389328161643457759676533857476790172453657474954912623939564692223095174 | None | ||
| xbar_smoke_slow_rsp | 37045872546517212429759420910837940381762065609822403707772019127059252010403 | None | ||
| xbar_random | 44096967475439865558750712043988449239360522435644726355546241847504378494691 | None | ||
| xbar_random_zero_delays | 16435027870608911755066676944376019042760014451520547636559527765503118750663 | None | ||
| xbar_random_large_delays | 88016347927251369577656613413968551531560642991634091020521366317555717843629 | None | ||
| xbar_random_slow_rsp | 60161314310212199837429712746901850728781438435778667461604485553471199235584 | None | ||
| xbar_access_same_device | 83070335129973526940937252248761341512508627570961108689225685541708969916634 | None | ||
| xbar_access_same_device_slow_rsp | 73308878531503314661332708160343407787217814928769246698114016255883065151613 | None | ||
| xbar_same_source | 59936413406867256176245220108642320873957555809158590811802146315107086141613 | None | ||
| xbar_error_random | 104126225202128449093361437396829135130326648640179366173749512415822635566458 | None | ||
| xbar_unmapped_addr | 103500408289249421935100435352938205123017793153265839089922728463409571949492 | None | ||
| xbar_error_and_unmapped_addr | 5562652423526171136307756559762703526822400711355782447967586646310411901607 | None | ||
| xbar_stress_all | 88791154412069651631575927501766539836063388773275974329766768049569924079977 | None | ||
| xbar_stress_all_with_rand_reset | 54914986306515869265973917832606560332327556546935094222405080781181096307164 | None | ||
| xbar_stress_all_with_error | 11372568830058727882026971089059682589597591938728222929789526361858441781067 | None | ||
| xbar_stress_all_with_reset_error | 15363685626529812858371402487359611269120868970789157060794075922377578629748 | None | ||
| chip_sw_all_escalation_resets | 3436884853501898350483324277702730193010480474174756728546514307676339776329 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 50979352693451263077080555538057979430008082500775863676697983338351499727040 | None | ||
| chip_tl_errors | 90781297342611326830707172021468974136952287893657903245247174422958707612452 | None | ||
| xbar_smoke | 11902432496221628281350127229627951506401195745070769396524779508580080114919 | None | ||
| xbar_smoke_zero_delays | 88577345192296214935942232619578032101252923834761267193101588534842317234345 | None | ||
| xbar_smoke_large_delays | 7692377299939163992233855109136245444598546163635867453708393315173436117242 | None | ||
| xbar_smoke_slow_rsp | 95928269948263985534108223977102646545008202264027773251735851755618651430512 | None | ||
| xbar_random | 114713965849788878850886712896233362359825743022306866880700586349890806387595 | None | ||
| xbar_random_zero_delays | 111569741259529324699580047551454242937459422832917738779116597231981305619794 | None | ||
| xbar_random_large_delays | 4801390802439261278590565151404380397376610874068298207781580240845893405878 | None | ||
| xbar_random_slow_rsp | 60129055223127526185792442457235515851417212219652732087990731619122116139811 | None | ||
| xbar_access_same_device | 54401759731569702153125213447237697758782679065497743453979523458847089249787 | None | ||
| xbar_access_same_device_slow_rsp | 34970098746203447133869254507059984641021793551580105841205800976257705379192 | None | ||
| xbar_same_source | 63012794885652600570900683252610368746240965903263380304019733100969130358751 | None | ||
| xbar_error_random | 57418477648625503380619711023666729793672165164018310177749395709134762628221 | None | ||
| xbar_unmapped_addr | 24759691678127057288196814150044309598082824524711959997687432949406383383300 | None | ||
| xbar_error_and_unmapped_addr | 49487817651692672990911111993897297996933018712312251283903406015699618069340 | None | ||
| xbar_stress_all | 26377269035768178348691031095412065628097328406054979357049662428485223865166 | None | ||
| xbar_stress_all_with_rand_reset | 113370120956094190303351667883640293484595979782459274482688754862984616979244 | None | ||
| xbar_stress_all_with_error | 25863390149470076972675204684816980584748453928596025948815633138254915852206 | None | ||
| xbar_stress_all_with_reset_error | 82299894437089035831877358049099007897617848654654210002108292006056167198419 | None | ||
| chip_sw_all_escalation_resets | 71184853606548782112492240193803341425398127249759589165286993836246432082878 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 108182702243711083402161032151332888524049384132481215905892032845854615732282 | None | ||
| xbar_smoke | 100278698079257271431458138065882673335905024858553753172982881075800311762470 | None | ||
| xbar_smoke_zero_delays | 29359856466367095801812951889689446616944650266248336872611737313264457425194 | None | ||
| xbar_smoke_large_delays | 9094754609675815363419404394498168132470501472755708353358724577296386310238 | None | ||
| xbar_smoke_slow_rsp | 10819922756593712477064595085503353319926921977773352520736493825916316630447 | None | ||
| xbar_random | 82774532643049879187649466692098547058142561816302522478794589404242766611931 | None | ||
| xbar_random_zero_delays | 51003796352223943559888857002495468502341468670276628374692494695862440532490 | None | ||
| xbar_random_large_delays | 115005240535655677186218158983819893297599781038333973240883617142110495775436 | None | ||
| xbar_random_slow_rsp | 99926030849042557955619993825867519526614783006823125510480970059484328833874 | None | ||
| xbar_access_same_device | 100553113888749284293853740914171764879568203922243979425265962019021320697316 | None | ||
| xbar_access_same_device_slow_rsp | 39260959692365331166260423168864178738636039502785688297444017816025613016678 | None | ||
| xbar_same_source | 92627957688234137776420233380425444777706366485409698169697531588851812701519 | None | ||
| xbar_error_random | 44373716374374329679725441758875259343658590912691317000723461457583704804032 | None | ||
| xbar_unmapped_addr | 92039294486530544958299959218530267210269198842029110200043523895453649130731 | None | ||
| xbar_error_and_unmapped_addr | 94442298652013197949925130343065388305288958170667530119982205968680407356961 | None | ||
| xbar_stress_all | 57977622806635241029671886265620554692135871831393558439384590077964268357289 | None | ||
| xbar_stress_all_with_rand_reset | 1666510442686741685482475245656190071965670513579034616182947438898405348277 | None | ||
| xbar_stress_all_with_error | 74154230337216749134468519651767446121608764786896061825596435324644889503281 | None | ||
| xbar_stress_all_with_reset_error | 112302911128430821215069538432748971341076435853602436527480234341321570005014 | None | ||
| chip_sw_all_escalation_resets | 59795354127433427013030786504325700773649279557512193255243082964799082602350 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 3021987141915590433595588695808076768908158819077166720194786962481732936202 | None | ||
| xbar_smoke | 46680939566187832261211556172428897865898950025521718542606618066583986054173 | None | ||
| xbar_smoke_zero_delays | 100042884466916523088262972603765977442579567667849746085191770542877636448048 | None | ||
| xbar_smoke_large_delays | 101174345397582176528414156233825096658578935525932089051300505631397553088616 | None | ||
| xbar_smoke_slow_rsp | 41998569436279929815492086369931706924461699341030743652941225237797425645721 | None | ||
| xbar_random | 53524933430617456106705428989425620927281462655117031789850687360506371177018 | None | ||
| xbar_random_zero_delays | 92625670350216638093772596592954135503066899197550332827857692717080078502853 | None | ||
| xbar_random_large_delays | 19603208095218694487022424321697464941865707204778856042008174944234890740901 | None | ||
| xbar_random_slow_rsp | 39585870686410182208579744234795947492516501430014946302432270319696347337399 | None | ||
| xbar_access_same_device | 96723437848646663552219765280729245356128509980949535118090531249792822288653 | None | ||
| xbar_access_same_device_slow_rsp | 51326120529295894060702318955141821820392135897598651583999651628761946043897 | None | ||
| xbar_same_source | 93032334899801959603817568013905943502393804497180576955766923415272484093964 | None | ||
| xbar_error_random | 85298001068233636571552462149816844469433179169561342724224569431928956589610 | None | ||
| xbar_unmapped_addr | 68804525704726782344662604450853192523568461729736398082173402432541735220463 | None | ||
| xbar_error_and_unmapped_addr | 51636393066545479375036923789381033766846085390000621824083642951246355935758 | None | ||
| xbar_stress_all | 110429315459793070982205556619694703097763129317758839793074169539899698165698 | None | ||
| xbar_stress_all_with_rand_reset | 55180707709829996589708582877221054573894749422724403407280353266894904833710 | None | ||
| xbar_stress_all_with_error | 61883981290909896386237677461792120960149736009022326791016618030474239124968 | None | ||
| xbar_stress_all_with_reset_error | 82718077705984135064212315911331368438754835518634548714517306113887500988620 | None | ||
| chip_sw_all_escalation_resets | 84159426516093176354629274902116058080186725167796077727487588913820120592388 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 84572522381702485412802095768299109624089237527578494918100066007983195033964 | None | ||
| xbar_smoke | 11887147630883848451083485202846755205669691930890730606748295539797222042421 | None | ||
| xbar_smoke_zero_delays | 101957009047390757628946309830929336610638116591680687032180583196027965821309 | None | ||
| xbar_smoke_large_delays | 73884498987750814610449420082124701391509389110330139109587361164065963586450 | None | ||
| xbar_smoke_slow_rsp | 17529624679331277323633777615956886405886515583501691430438263200501598297202 | None | ||
| xbar_random | 94095013416896367710450781067577017784512872642710058237407258825622043793955 | None | ||
| xbar_random_zero_delays | 106231530354395306186351723821741362932887697538203994290464934908708623356745 | None | ||
| xbar_random_large_delays | 53825724882643351131125873627820870836909142130290926255687269515619124114767 | None | ||
| xbar_random_slow_rsp | 41277365083047148058344323525937003358018787493233938144888374116597244371116 | None | ||
| xbar_access_same_device | 36666813625932453452783504227376202746369216389960978602116554428208674974192 | None | ||
| xbar_access_same_device_slow_rsp | 87726284022245192601749319604900015510001700343317197566226590690844918170122 | None | ||
| xbar_same_source | 47098234686738309016820160878918472726930791822965012672727731449074100857221 | None | ||
| xbar_error_random | 98242138075042823347691565468861848772134669313904824505067374164240679550403 | None | ||
| xbar_unmapped_addr | 101515486055874800503324980049187020195478017348565519165196390064483422876992 | None | ||
| xbar_error_and_unmapped_addr | 8092303431860130548410153762823028841392567860018072789504597076603749935943 | None | ||
| xbar_stress_all | 82227582730022671767883770969829834744910904353066791111321231671130608728300 | None | ||
| xbar_stress_all_with_rand_reset | 114182152747598264225899885467327076480091903028084949443816202498093929368152 | None | ||
| xbar_stress_all_with_error | 111135524154646358383608558114230499651468285111055984348070394275672650575437 | None | ||
| xbar_stress_all_with_reset_error | 85000591862957657601097010303106988309035097097561382609277895733864798610079 | None | ||
| chip_sw_all_escalation_resets | 30814383529685964958662572226758098785280357408450255512267733812964436216139 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 42731052812804318130737522374832170874659059673558610804854057470476778359001 | None | ||
| xbar_smoke | 25265995315491983544760942734239362568955035333107778660226540518871135656124 | None | ||
| xbar_smoke_zero_delays | 36470338631787833884617007491000481064477784756599587584569773378429202403813 | None | ||
| xbar_smoke_large_delays | 3778177167785307388895699489535753747588406204232076082742369500277765036764 | None | ||
| xbar_smoke_slow_rsp | 115596699841864073314539028147157907118781869020239243934345777459264781490384 | None | ||
| xbar_random | 75493707423064917608615597921370958781123856211330346552965839996913216558867 | None | ||
| xbar_random_zero_delays | 34760408610212624484350959088404766140685266370833094844462381674485929182646 | None | ||
| xbar_random_large_delays | 60113801850423183193265542208063783143310024303740055977508389024986780082148 | None | ||
| xbar_random_slow_rsp | 106098248111641705090632591565354979257571184278389105434984449051562702005781 | None | ||
| xbar_access_same_device | 96274805187819037844127678388689823119142488271448031815420315808920548915193 | None | ||
| xbar_access_same_device_slow_rsp | 56294959487083883772881740734910709277590046640483423284981878290679072552869 | None | ||
| xbar_same_source | 53268955885105316894039144828865707607196143543376211052683287773965263251593 | None | ||
| xbar_error_random | 27008835877701321260248540158460073801101199248359567218493285899396256754592 | None | ||
| xbar_unmapped_addr | 61726505492854382997970175608513437885857087785499790044081270173945666647527 | None | ||
| xbar_error_and_unmapped_addr | 107268427158273535475332337355033299166540980080144800149357427849322335037477 | None | ||
| xbar_stress_all | 42520553562565116636550954660252207915361843259117741201983398150079293673381 | None | ||
| xbar_stress_all_with_rand_reset | 26392005993088179934359444034805889007358259837199665619525922605997986709208 | None | ||
| xbar_stress_all_with_error | 22967783538632368599836784627505910031745765956198572379405674413574299472218 | None | ||
| xbar_stress_all_with_reset_error | 71933295106444792490058697617468117136228785448077643478663137253125235608576 | None | ||
| chip_sw_all_escalation_resets | 86326634301138745673405181690783027893164153047575890973765051736827205219022 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 83888201844251393252188242273349062354772561563101717534850663289314579170482 | None | ||
| xbar_smoke | 29559085328604315649505760532162629126612989350054804112530572884802352673231 | None | ||
| xbar_smoke_zero_delays | 109428418344532519413863250006712355760731593981174126277294263892287515854479 | None | ||
| xbar_smoke_large_delays | 21188157655661653006905610233857185120551764813420523440025185285715384433824 | None | ||
| xbar_smoke_slow_rsp | 85183627488726003163712432367011300881695109469885340462143282031763376246035 | None | ||
| xbar_random | 70747122734628628429423974247443798052229298212099413527148901483283898433565 | None | ||
| xbar_random_zero_delays | 16358496604790875774067899926769860075833509660843987294677533839043844961348 | None | ||
| xbar_random_large_delays | 110160036173829602487203773309961710289012617415467925878416644058620878602105 | None | ||
| xbar_random_slow_rsp | 93053191575757091589898647444496617167149444368125619556819242835840687120159 | None | ||
| xbar_access_same_device | 94300709416522907934345798226753994961346267264853542700920646253322807841811 | None | ||
| xbar_access_same_device_slow_rsp | 66297632464320399728527167657752815933396472811664165837582697013687004473134 | None | ||
| xbar_same_source | 20751948398876682906066143197163319080153206513380132489945195075161727430219 | None | ||
| xbar_error_random | 95961064000389713599717578937646092956115016094493685313044961073323814547934 | None | ||
| xbar_unmapped_addr | 105129593139391718038208538854507288678932926381784185735688573113319969912539 | None | ||
| xbar_error_and_unmapped_addr | 1403852379506728974692557059712777666109051081361165340740842321182347484418 | None | ||
| xbar_stress_all | 100109934392830237882782302585505442827566267057445382447599219232841578523419 | None | ||
| xbar_stress_all_with_rand_reset | 75553287007742334593670418589696017624454880453935844384214427076258881670326 | None | ||
| xbar_stress_all_with_error | 12687935272306673590955792352059756270395866546541511210177099351869165274026 | None | ||
| xbar_stress_all_with_reset_error | 80665512350166097436787122829783318393042777194525786386113671614378046949053 | None | ||
| chip_sw_all_escalation_resets | 81511846359782304840828104407686406842143550650752706182827901832131213850737 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 23476067445419616148378962187836723390602932863443696329370643936703112698007 | None | ||
| xbar_smoke | 52909797934910662836898252744815570589421273562706270910392737526937318957121 | None | ||
| xbar_smoke_zero_delays | 96538103375469832127003411914326175865380850165692383042210177320204672918971 | None | ||
| xbar_smoke_large_delays | 11261810844711282041698490438347222519659429574402155807720299357175437267547 | None | ||
| xbar_smoke_slow_rsp | 2854253423309661102056575729739879478136361970430801361572144929736609098165 | None | ||
| xbar_random | 112026392492871208220713596856803542753525484260930272887553240768365428260667 | None | ||
| xbar_random_zero_delays | 106501803705844468150078779832916251832215050865733806620827995698132409036064 | None | ||
| xbar_random_large_delays | 21841251930325598891333100852926682513975083070829229439124271498733677553795 | None | ||
| xbar_random_slow_rsp | 111519385978775017060217936865768538431487549625131337270091641290244085100011 | None | ||
| xbar_access_same_device | 16279325899321231630173532435759564025747245738809014122046200924324956928268 | None | ||
| xbar_access_same_device_slow_rsp | 85238268586385834888754304034877981297360834765201494664763919729525343044626 | None | ||
| xbar_same_source | 115496529392383544386124665465043373598033609104581290127177690020843950666412 | None | ||
| xbar_error_random | 17488557764481758946925353701065283889941106282549963221497316723156652461840 | None | ||
| xbar_unmapped_addr | 80502617735769091117930934716827150403198726159038755351082851157193264133387 | None | ||
| xbar_error_and_unmapped_addr | 108059545711438852369089719906854824774605057980507251301518941090767424053321 | None | ||
| xbar_stress_all | 98760152967568688806848582311684091484823350599406745158443476076586628491541 | None | ||
| xbar_stress_all_with_rand_reset | 30991842735320549138766449001729902445427770409917623379791486941279671051566 | None | ||
| xbar_stress_all_with_error | 27438016806100632745364149777569164524033257399951597885092926337807445519891 | None | ||
| xbar_stress_all_with_reset_error | 6472760072476143334839496066755367703942721458124060030087540524615734663854 | None | ||
| chip_sw_all_escalation_resets | 53337884498747227359239993104326065834672510204141703830400412414288957737037 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 95052430323928473406289270803306794254154485666556550264617921010339299923976 | None | ||
| xbar_smoke | 96078184743470615209647712226388679492626233837102827871387188770278047042224 | None | ||
| xbar_smoke_zero_delays | 69626425540868406563996419917440855932507512055970586898288538124393877665373 | None | ||
| xbar_smoke_large_delays | 5127580273625221878849750539812197389954194003313473319390302284994937112862 | None | ||
| xbar_smoke_slow_rsp | 106607983698242541886787161978224017295733616936590883658144584734046862160659 | None | ||
| xbar_random | 32740199276725031087704393777145507705767967163338385449493744699126754462495 | None | ||
| xbar_random_zero_delays | 73743643396824917478411320220511681843164225541629120558727640126909356578491 | None | ||
| xbar_random_large_delays | 12227866370752160466502290148264615950576003264582067266459577540825395269786 | None | ||
| xbar_random_slow_rsp | 97439297267151998291559513209016604679308951911807127952134677073044933225118 | None | ||
| xbar_access_same_device | 6110030995570955638729440748758117228303852437352676318551702274443878042939 | None | ||
| xbar_access_same_device_slow_rsp | 89374287281417812956557147136343372180484290453373116541074316114265111340755 | None | ||
| xbar_same_source | 69124616595433808119838818682522683980031054676958252188284620111206676451787 | None | ||
| xbar_error_random | 88152584434447845229277154991922737275559292269642035498902496869157357126904 | None | ||
| xbar_unmapped_addr | 99783032332855046529158564664118531283057524001385228119356608892167479916873 | None | ||
| xbar_error_and_unmapped_addr | 29336846035984731660044726478531952687578820704320122294228852296889928127010 | None | ||
| xbar_stress_all | 15002308475492144136808251760526732737770516343716214469353209138762051862305 | None | ||
| xbar_stress_all_with_rand_reset | 74343765771328377468131245655210149606135923568916727898352605630940231106220 | None | ||
| xbar_stress_all_with_error | 71356127048567847634952004563063264368145100019231182252950593404760972867604 | None | ||
| xbar_stress_all_with_reset_error | 88924706726769178232432717971698334198253707221760702562988713906732885017688 | None | ||
| chip_sw_all_escalation_resets | 86140126117664171413039814189170029810326109894617344567836814802137910384748 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 79294363069660991867025131870198355560722526604101686870889627605037800818771 | None | ||
| xbar_smoke | 98907481485627305312943273937998040645197385761081054657879974864161617315220 | None | ||
| xbar_smoke_zero_delays | 111178650180190609189899751768099437098056343457596197574142883470473300850383 | None | ||
| xbar_smoke_large_delays | 95001173135169865835808616159917404915883909053731341195968925050392536551633 | None | ||
| xbar_smoke_slow_rsp | 30700028051578762213519250922480004167247285292839903033824921187086858699763 | None | ||
| xbar_random | 87892370820490631108838445615370941927071141656770857320349268362758375557401 | None | ||
| xbar_random_zero_delays | 94508542863140086520494942089470331893061937591829249804468279025192607874206 | None | ||
| xbar_random_large_delays | 84202882625435785013692296972809396579549442686132461561030716159628920193348 | None | ||
| xbar_random_slow_rsp | 38421917638055912372850245395309609066265628890831652061354411287771077646921 | None | ||
| xbar_access_same_device | 21387557275762642758923372169703961111615900291735259983002536369272664491495 | None | ||
| xbar_access_same_device_slow_rsp | 77556086666799288774815521600485477373409773690625047035261569224328678943149 | None | ||
| xbar_same_source | 108777158999615263466844072184621683977241446311506959506362751741768667671670 | None | ||
| xbar_error_random | 41589812978235003205769477734064293119714334102892533285942427962957235179704 | None | ||
| xbar_unmapped_addr | 99452372432881178559044932410139292749320986860528238683321589089178222991278 | None | ||
| xbar_error_and_unmapped_addr | 64438392685607076149543350622309341620208402719734255575690295192360595651604 | None | ||
| xbar_stress_all | 28078418990614762244862024807846463770770087284444296994409667821463331393115 | None | ||
| xbar_stress_all_with_rand_reset | 97725504983736247715039320760990934069145369210256515898825141404627561185945 | None | ||
| xbar_stress_all_with_error | 72885136445666665919088110533459544126394031684961901518893834290235962093788 | None | ||
| xbar_stress_all_with_reset_error | 38146260828817900221517598597703697306812713259565297841289276421844355663197 | None | ||
| chip_sw_all_escalation_resets | 83460846707764001257075046149898167560816178275667170486546220888304236684811 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 93923979229468009913491578914071918561749329053235048786016798169208308876339 | None | ||
| xbar_smoke | 95665680317338957162008083109573650040654021772934593812699091802805172494969 | None | ||
| xbar_smoke_zero_delays | 13805592438547330382693289632859931685054630315006402795795087758775116344368 | None | ||
| xbar_smoke_large_delays | 31932592464012449348318145781399241087738001985877032638378834677998240532410 | None | ||
| xbar_smoke_slow_rsp | 32869957631640597258682304240578432643147417012618815242582768131086816417334 | None | ||
| xbar_random | 46023898822796175592734686758538795707228683327041950082843584744384848187528 | None | ||
| xbar_random_zero_delays | 71709247280635428430839543895720097301548570388675662435196945907509774573071 | None | ||
| xbar_random_large_delays | 39548625662932643973890155744320328852119605634927505911035705213877481797540 | None | ||
| xbar_random_slow_rsp | 4517593890458522841398722737291217189444084062668901025011518196879260050261 | None | ||
| xbar_access_same_device | 2611322093132583824081809457760799421425627253392003865853188291312686393926 | None | ||
| xbar_access_same_device_slow_rsp | 57570326775662791916068671920663572864710947984381502333166373761052274244234 | None | ||
| xbar_same_source | 105396566660662229859115631396556784391868928588364736223225581461997952888610 | None | ||
| xbar_error_random | 94227210239775623254257155646170867039848193451624796597519424695884727589030 | None | ||
| xbar_unmapped_addr | 75529778380411020770867384110406897151375977085037460708730343189035063975756 | None | ||
| xbar_error_and_unmapped_addr | 62627337828020143648882759103085725136632430090127568716360818789733520790524 | None | ||
| xbar_stress_all | 67754629817707931153535374851927203832818919059243680626390521660601772931959 | None | ||
| xbar_stress_all_with_rand_reset | 97218778367606318143192618478587220606118511318303909712992424565607599858344 | None | ||
| xbar_stress_all_with_error | 2133207843481208652933615518607747871575830790807002206881537114411467111203 | None | ||
| xbar_stress_all_with_reset_error | 3419817721075478686820800085600979859484960090290562225675706556542471808798 | None | ||
| chip_sw_all_escalation_resets | 76005986930150637781791770944357960953711286894527113561429036687388400363616 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 6993659480303992641973911874670089142220977888921861820029566478218388330966 | None | ||
| xbar_smoke | 38855843871370531293433324739334638703045346304450870299262121328336662403666 | None | ||
| xbar_smoke_zero_delays | 73785017357806727164259670899007518156138699903894289051801359679214522736253 | None | ||
| xbar_smoke_large_delays | 5250756523570958567978945555011771494855609678842415311371514731699628102196 | None | ||
| xbar_smoke_slow_rsp | 76073994563546156926317022251766239926193446646500888292438039333455925253907 | None | ||
| xbar_random | 7947372222007922619782045891103472139344854492982246706997701520921265316207 | None | ||
| xbar_random_zero_delays | 23553564664406488358646660895894498421811320168014726340889776013815968579337 | None | ||
| xbar_random_large_delays | 115152887055364255914962881598053904089776187611449812985600607983731418636077 | None | ||
| xbar_random_slow_rsp | 91358270336522023172616901547646580920237412317809913162484887110079262294306 | None | ||
| xbar_access_same_device | 15886485858841597378925935021761491294585589064390763399177000569513419403597 | None | ||
| xbar_access_same_device_slow_rsp | 22032644984949015152664739476133610813388633685836061288019691557280534493839 | None | ||
| xbar_same_source | 101042608175463169236968323777250642611218445456337995066111748536047407194943 | None | ||
| xbar_error_random | 96086908512687460291892973410991570451158481457829712866753469506950549278014 | None | ||
| xbar_unmapped_addr | 6569641789761680971272204935981389069666039481930045152478855630959261139281 | None | ||
| xbar_error_and_unmapped_addr | 46363694952699357074803525679327536533232597270580676749776167021057198295103 | None | ||
| xbar_stress_all | 31234664381356582400810921049489955666783080356968042873137238966657931392763 | None | ||
| xbar_stress_all_with_rand_reset | 79050672698246167547409991037557298181769057934170047816804513784496642231564 | None | ||
| xbar_stress_all_with_error | 59051185469082460678490992416412790601323345631115422923042908340275638147171 | None | ||
| xbar_stress_all_with_reset_error | 14879820211567323077394648031943954124510364272887361398674867077933927636680 | None | ||
| chip_sw_all_escalation_resets | 46339976382446847545031482578124399075335172384158571019604137676378307373709 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 13615828919500280804790435208867605852044889657031422017681073590403431410518 | None | ||
| xbar_smoke | 72255521807994998616620669924283676892348888449887256184065848020966005219804 | None | ||
| xbar_smoke_zero_delays | 31624439221242639362479808075500023519829089208216448226040209048621768688386 | None | ||
| xbar_smoke_large_delays | 108845514620234493807920788183791191336120872200832316698014136620887576871006 | None | ||
| xbar_smoke_slow_rsp | 98271645137849899543227126192193114182893609795442425996964712937795566496915 | None | ||
| xbar_random | 53407207434083254725882400872566530087257747486834490957839630129603552965081 | None | ||
| xbar_random_zero_delays | 84063859377875366019991257642283152792135545654964086040604315830185243880472 | None | ||
| xbar_random_large_delays | 11917725678118763700043642099833890228022249848833990300392156370910596017011 | None | ||
| xbar_random_slow_rsp | 50704011536959610147713010197793798833839926064315485323129666407889047597365 | None | ||
| xbar_access_same_device | 45548911356911668103048326131104483353145630217659829058497639128931912630524 | None | ||
| xbar_access_same_device_slow_rsp | 35035617921133784188158896329640438564672723612364156296108464501813118479922 | None | ||
| xbar_same_source | 113012002363885441268289767679970849964005513696114375462867717405276896948313 | None | ||
| xbar_error_random | 12434323401664809540238543022826148543268275318181178472855186725558058000080 | None | ||
| xbar_unmapped_addr | 108090498131624714720526600146796407601524413174273645674798950027040583138852 | None | ||
| xbar_error_and_unmapped_addr | 26722558295077917223571140534090204155602591132922183613818834698445149305770 | None | ||
| xbar_stress_all | 46844828137286894671114375983197061366718926147028653759826071461153168379789 | None | ||
| xbar_stress_all_with_rand_reset | 51931505272868203457678136281209269329820080716416510672329512302369323895275 | None | ||
| xbar_stress_all_with_error | 45074560175780198279594622408472157273354704002853792779990030912132621863557 | None | ||
| xbar_stress_all_with_reset_error | 113427951634458695544298419609157493449070400954337176731095812779265882117675 | None | ||
| chip_sw_all_escalation_resets | 52475718794828503502941377256256336432181449534040170217559948213059101658035 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 51237481924938325248897402313107007866128695975934785817115525941220919927379 | None | ||
| xbar_smoke | 11484594646947219516731487224382104181633849382266192368235653238565060573731 | None | ||
| xbar_smoke_zero_delays | 786890289506800612973140223729586220323389467931164541499959762320322788108 | None | ||
| xbar_smoke_large_delays | 60719163188999367508343901756221499048844734161601983159625419309000012812689 | None | ||
| xbar_smoke_slow_rsp | 89678456080519330701522192586155800649468075531866717751872265772851642249089 | None | ||
| xbar_random | 36720355030923718245393902637559872563701877444134759285502967386932544527522 | None | ||
| xbar_random_zero_delays | 76625566473617856484963531992751868833832933642356017842583782927743667214051 | None | ||
| xbar_random_large_delays | 81474794905663399491223648842082873004484289651584618403546406896627018459787 | None | ||
| xbar_random_slow_rsp | 81071985595937953855989232345003774610736584318134530646545872063086538837742 | None | ||
| xbar_access_same_device | 4233294577694708265346678787751446777943889259603167880674077122048987873026 | None | ||
| xbar_access_same_device_slow_rsp | 97659124256706663906006523693266193583384228388684901644951962669066398017628 | None | ||
| xbar_same_source | 70058174826850986429448092860981971979491274397512895532113682478533723387309 | None | ||
| xbar_error_random | 57782745178641711361948720245958389794701094939217452409844492336117966505911 | None | ||
| xbar_unmapped_addr | 74825991705366617416838706421518052178286714238524432684908165130828599648513 | None | ||
| xbar_error_and_unmapped_addr | 37463063877974048353929932362210387048802453510834854468005830060923473652228 | None | ||
| xbar_stress_all | 101158920061933086808736335787511800055018041311211575089634330998288085896115 | None | ||
| xbar_stress_all_with_rand_reset | 79823216324137623935337732878809446209117167581463558504069938015385310047809 | None | ||
| xbar_stress_all_with_error | 49938827082540364912518173646847668234773368632042629436483908635763890197035 | None | ||
| xbar_stress_all_with_reset_error | 82521856450458403408846760967910955222299716221976210842754947467687003216761 | None | ||
| chip_sw_all_escalation_resets | 58882374463019175782286692595868115520444923837541957146574160462646987442618 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 87701611233642875473353696309907578969203723130546883088625737051431493713340 | None | ||
| xbar_smoke | 28185742867051354187990220609540437739561350240387583577234759233697664027717 | None | ||
| xbar_smoke_zero_delays | 23303680641784326021690706389577617200860117298602212301347767023606230353570 | None | ||
| xbar_smoke_large_delays | 70644404874667008855421454870802907699022207488554326244341452390697028879811 | None | ||
| xbar_smoke_slow_rsp | 65287874594116477702001310085094172498528780824401000809858726339397807140289 | None | ||
| xbar_random | 47956053525022072511720133450818377875159575293820583719524619273358865298084 | None | ||
| xbar_random_zero_delays | 108836339232243554028308070245213896732688152162832845602866800532149989950637 | None | ||
| xbar_random_large_delays | 54795251263677270158409254173618309349476122456127953769066219733223167754379 | None | ||
| xbar_random_slow_rsp | 74307783827677547323923268918511472763222845424127324460194006916241772290532 | None | ||
| xbar_access_same_device | 105138202012135734210116342621844030064971652759984630154832823326891514204869 | None | ||
| xbar_access_same_device_slow_rsp | 7662158880970442154078951638840218172194454895621767685580709568919881320162 | None | ||
| xbar_same_source | 111081331124672941944063285094187171652022065127716476050782420458404928688428 | None | ||
| xbar_error_random | 22433651140332059935940972178318352866243879767288163114144392351446751079880 | None | ||
| xbar_unmapped_addr | 1841563018282037394026585260121830734148942998376989455689432667636192322915 | None | ||
| xbar_error_and_unmapped_addr | 71579654887977854808912234761960643362840019960865154451338954812189729378151 | None | ||
| xbar_stress_all | 84233800140574000586517183897154509489062196991229596199777738161916792214995 | None | ||
| xbar_stress_all_with_rand_reset | 67336799752892204391760848064985938895850370764971952770043389003735357520031 | None | ||
| xbar_stress_all_with_error | 59108015170117392296359079994968786568360779035020672278243510926641772017156 | None | ||
| xbar_stress_all_with_reset_error | 46919224185022948800184514586672324775136850203097334984770180629488593685571 | None | ||
| chip_sw_all_escalation_resets | 73149689273147285424252709632481943281694345811611274385501856827704325386680 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 25692138247423627368472043721150152601653893300288208884780478960933468574884 | None | ||
| xbar_smoke | 114195339341938341162505703867768021347493468213080815961887273609717341297057 | None | ||
| xbar_smoke_zero_delays | 38979162451428300690980198256276394072643869055841676132814946939661011221265 | None | ||
| xbar_smoke_large_delays | 66667232466379278877829725609976362013757258997544433266143366055862715490812 | None | ||
| xbar_smoke_slow_rsp | 62470080615680170766603260121060654012709399317157679137585789580311440996817 | None | ||
| xbar_random | 107389656859659860041565483136092988731801087248952432408290242380100498268474 | None | ||
| xbar_random_zero_delays | 32287810080176081387780798471049619083982317322066389803033491473264961287279 | None | ||
| xbar_random_large_delays | 67803987323672877359458553868422929247924796537127958425313425347040860789412 | None | ||
| xbar_random_slow_rsp | 51313357636576636532102621767675018273164053530189751310400163153629439878336 | None | ||
| xbar_access_same_device | 110873358423565021771290945801922574541457780139858268032830272952721438926889 | None | ||
| xbar_access_same_device_slow_rsp | 30040383725667078100000265653105522224049921565859965324628429420689840061529 | None | ||
| xbar_same_source | 112548186396420002006120136127255069478265270375598231907224234745379290275032 | None | ||
| xbar_error_random | 12452400846316808266535245238251295638670638637512884342401294690792750652823 | None | ||
| xbar_unmapped_addr | 11095741228292790135249639602514721872228610756081989895818920329269686784959 | None | ||
| xbar_error_and_unmapped_addr | 43128933835833879708486627634589877932490907590529495881787580816522939886678 | None | ||
| xbar_stress_all | 100231644348425887994235599658370084548327679210565558115940141504874887714640 | None | ||
| xbar_stress_all_with_rand_reset | 99361619043413558504465510555149284433008793333687695452483281649872256807399 | None | ||
| xbar_stress_all_with_error | 26722786021172059190402766327304798564818735013588925942339467714253595856395 | None | ||
| xbar_stress_all_with_reset_error | 77855748247207421265633589772552006506193759763618455155210234252478949227020 | None | ||
| chip_sw_all_escalation_resets | 107924761754653193358754744211479791275201608439980434246559802071896525768693 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 34400938235707467474900994993183522759596321439515926275894117979968686664780 | None | ||
| xbar_smoke | 1492131081331066097610410040048414556238720602259050120110428068840714926289 | None | ||
| xbar_smoke_zero_delays | 60130462090853880766315771240396034545841146335824763191866635722437011998706 | None | ||
| xbar_smoke_large_delays | 3301138879404491210858804737792003689503886334997611699898380006769371384166 | None | ||
| xbar_smoke_slow_rsp | 96314404175922931295598088340058565136020840123838864497515547049803385145186 | None | ||
| xbar_random | 39016362483627895270262659504271840713925472113682260215864057205971082296890 | None | ||
| xbar_random_zero_delays | 78234977086794579513070596653999631191879980561515946853429205069264060321525 | None | ||
| xbar_random_large_delays | 101299291759022540748472634501248973169412447918570523951125860570341404542495 | None | ||
| xbar_random_slow_rsp | 35730470061750002731441299354810820563157900656965092622024177428156702089844 | None | ||
| xbar_access_same_device | 68473122433756807656326950659248744228300433150757817724375892947018908911460 | None | ||
| xbar_access_same_device_slow_rsp | 8878835538486120073360455992813940415943135190074459806010639313406428218907 | None | ||
| xbar_same_source | 55380519635769511085066480370491895778529885033380052866979613052114855607456 | None | ||
| xbar_error_random | 77116598629234101966002199532762970257068139713829186505889237725570311236614 | None | ||
| xbar_unmapped_addr | 5116363627941916492753052571981152373166717589041713826839754847990610733046 | None | ||
| xbar_error_and_unmapped_addr | 26779270826903909498606041018651079577496055484279768308736330456390237163982 | None | ||
| xbar_stress_all | 7896673450435884320887565938725224446403941464924592125049072857015799503000 | None | ||
| xbar_stress_all_with_rand_reset | 31165839368753088851905715344233715645006749379340576285248751448841139628699 | None | ||
| xbar_stress_all_with_error | 79417473654207255354416123109867266272861055696153059973628195641239111749914 | None | ||
| xbar_stress_all_with_reset_error | 56098840184767046080003745358860342714203709991264363023464861621064305737347 | None | ||
| chip_sw_all_escalation_resets | 71117396272601816288365545404992319557580690176084267287288717610852182614609 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 101356689383596686182961337314022892324475107549069473025664538382522089104295 | None | ||
| xbar_smoke | 6134329881156993143409209575640681268047572586691884012813874404011034663306 | None | ||
| xbar_smoke_zero_delays | 404309064275051865273260010094299878920124622937506982962085622918055797786 | None | ||
| xbar_smoke_large_delays | 26792373739118127384814429664415802232752409252860910924584903020249717637914 | None | ||
| xbar_smoke_slow_rsp | 89486045103438033165211328851409226778612391768974903993560605584205524082711 | None | ||
| xbar_random | 101114788632881790436698510553217173303484999105743859650740920319761403413045 | None | ||
| xbar_random_zero_delays | 71065341590285575758475539312328558605531316866932106065587441167211868483636 | None | ||
| xbar_random_large_delays | 14936953585786001181549912179085790132477264499186661372509950983600164988867 | None | ||
| xbar_random_slow_rsp | 93737031047359693011758711123565564255597159241716830896015202511686858180265 | None | ||
| xbar_access_same_device | 19527929841323047923824831365400374230869366781783172131758606597077160448927 | None | ||
| xbar_access_same_device_slow_rsp | 109627612530986649026148483608925748772157675626959438175474320327114463408118 | None | ||
| xbar_same_source | 24148409520826661130605308623268860496674428358426010715212684811999758181282 | None | ||
| xbar_error_random | 54348553971967160213987872904090111860609325558477748203409277320581331063136 | None | ||
| xbar_unmapped_addr | 52309490435356825099238597433306580891497721597748545872657441478586901262619 | None | ||
| xbar_error_and_unmapped_addr | 1425769581630633924267286786808045223958194815226118716596847808194196941247 | None | ||
| xbar_stress_all | 91256787024289356438274874385692684977679086417570623246538483114651643167679 | None | ||
| xbar_stress_all_with_rand_reset | 27780428197572708490294786260474835549388750520347088209161025130759277897832 | None | ||
| xbar_stress_all_with_error | 62834543417224299952056885870500367534565025320625655887222417533671759377938 | None | ||
| xbar_stress_all_with_reset_error | 39749715628972774910315613214334786161335616113201454779987506164759119886994 | None | ||
| chip_sw_all_escalation_resets | 26328874842440429961192689678980204727814874371080730715007935671115295321986 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 45448134294088727664159938919526016182308071540549039906388293012399209875344 | None | ||
| xbar_smoke | 35256052663190059178888264106155235753522123373647748272903762157099783402966 | None | ||
| xbar_smoke_zero_delays | 77389919523587590526033000954862905398211094381286891178097496264826909021188 | None | ||
| xbar_smoke_large_delays | 7410888338983490003248243745109935980927595551668232292087004945692693546317 | None | ||
| xbar_smoke_slow_rsp | 37085084232220664152194014932006917811673157909980366785424636263385489557889 | None | ||
| xbar_random | 35236579406351565784838898366871724419878171199874079216343711173144700694792 | None | ||
| xbar_random_zero_delays | 326324777675894105764056807084696328894046060846867804817634756642335118415 | None | ||
| xbar_random_large_delays | 10554840453887813317201566520595111795988320930936684739861420645801172864948 | None | ||
| xbar_random_slow_rsp | 26461510621106261063668491619294018108014899522172162618818139131631807938917 | None | ||
| xbar_access_same_device | 109901504173639515149687244873599113162068889286579654082952504177017560012169 | None | ||
| xbar_access_same_device_slow_rsp | 2440966683321388676357489709886212096381180313019366972298300801630520954411 | None | ||
| xbar_same_source | 105466257019978950341065527257612142023662677071082962188509726338306172157932 | None | ||
| xbar_error_random | 37218074244038633301999563967437698545120821903317381222147654171185485442869 | None | ||
| xbar_unmapped_addr | 14483310275989665026516060822355989847363937419492483992338737337837244665213 | None | ||
| xbar_error_and_unmapped_addr | 37806315504940509682361855305834488944082345363458969702106771458625004340739 | None | ||
| xbar_stress_all | 29987254562275063191935039911490661131961411923822818427500924433183276145192 | None | ||
| xbar_stress_all_with_rand_reset | 103787009405349253707186548848619733177148668204993667239831321807459606224829 | None | ||
| xbar_stress_all_with_error | 55996413776835757417396754384404012310344855372629364891284357754756519804844 | None | ||
| xbar_stress_all_with_reset_error | 36886048467529867325192316692001138155625528978130872434804277759029310990368 | None | ||
| chip_sw_all_escalation_resets | 27156007630205365843466402411147309834772509840169429806345475790684683520386 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 7128491115428803832920940645435916535198217368587789758813592819097888251790 | None | ||
| xbar_smoke | 109506942056071321228775406282678516464193007180328987413290800689047592905479 | None | ||
| xbar_smoke_zero_delays | 79305823295113262954925462626872090630128426221900026159755855054150931594518 | None | ||
| xbar_smoke_large_delays | 37758906300830454492217138472658219313685771144001747196878675227622440126105 | None | ||
| xbar_smoke_slow_rsp | 51540169040355311609133450847782243487155118694226722165094317144548294755490 | None | ||
| xbar_random | 54920750099828019191706535436189494701438689833047290535399940058044977285089 | None | ||
| xbar_random_zero_delays | 9598453735120113357484798731732599843124375210343924262605697384599865800697 | None | ||
| xbar_random_large_delays | 48069070690483462591982398300099485485434901970910802162857174780653126640305 | None | ||
| xbar_random_slow_rsp | 65752446294584863098827103478924377162132507357478576598124349394801752725664 | None | ||
| xbar_access_same_device | 25871396829147928024461747991249501113729198548503294268343690851710599051287 | None | ||
| xbar_access_same_device_slow_rsp | 18355152476520475571081395350319456061157016137714240538256264789813903524 | None | ||
| xbar_same_source | 92316021155740773153429069492332084244416584853026252453708477686654358084678 | None | ||
| xbar_error_random | 25876882057940740780995898525984290844188936953992623054234161898317555584167 | None | ||
| xbar_unmapped_addr | 107621817117071752582592381504513035520498714685980039561756646842691908941518 | None | ||
| xbar_error_and_unmapped_addr | 88599018121316879990235807631010697489466596092761406775619084610311048013245 | None | ||
| xbar_stress_all | 80106169110613860110329618934214115563828457253211207072688327704454830410127 | None | ||
| xbar_stress_all_with_rand_reset | 29726347739040019279248896741608749322846965425797684803390584640019172012268 | None | ||
| xbar_stress_all_with_error | 72476338177241980800694145400052335188116949718731802704583662926084079143832 | None | ||
| xbar_stress_all_with_reset_error | 53875744076161395801504930877379886568202561660769274628417067041049719231045 | None | ||
| chip_sw_all_escalation_resets | 17982125572739911362290884013836853702289511123168024665157395425151881083533 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 90694704284818633570960435738183721492740232612103613429761653042946093447054 | None | ||
| xbar_smoke | 98230327792348931117885491814081441938735206835775512996848827367106111881396 | None | ||
| xbar_smoke_zero_delays | 14738599241876257356250953623585536445892333096887909847006491261456081669248 | None | ||
| xbar_smoke_large_delays | 94610670906856339551531432489143033280276850486044267073336772342015755682232 | None | ||
| xbar_smoke_slow_rsp | 68299994079146798206370454571676421018808023489553692958465208636169647887216 | None | ||
| xbar_random | 69704001899830100225265587695188948677106606702908725862146944358229712036343 | None | ||
| xbar_random_zero_delays | 61916442048266393371647854922363013623408453870694948890440018144071524523335 | None | ||
| xbar_random_large_delays | 28286866073089320356925159932700541857059234337915953748445174273450563810050 | None | ||
| xbar_random_slow_rsp | 92188663419039457108287257312884949256845268219181918918871232770038656462693 | None | ||
| xbar_access_same_device | 1229338852166576469987664113967618924373674733049371908508839460693653955189 | None | ||
| xbar_access_same_device_slow_rsp | 5320504575465361652950179929783589904303611618889305274734787018496284868174 | None | ||
| xbar_same_source | 101211242995484699734991153931745106851280102585217991340882294191477648684642 | None | ||
| xbar_error_random | 86589065374090261231309472626701007534686727789800124758937456382152781636007 | None | ||
| xbar_unmapped_addr | 31763115814472264218110457151449002843116229711913077535884736331356246796774 | None | ||
| xbar_error_and_unmapped_addr | 26809457566164313703435400321008765155053344462749502276462827834377470488558 | None | ||
| xbar_stress_all | 65534745979714050153411138959661497253958493395282831097673551504488983512854 | None | ||
| xbar_stress_all_with_rand_reset | 107177865599401502798590929835287742078908890645388473357799832884811529494535 | None | ||
| xbar_stress_all_with_error | 58680188344707194136671571308785234504960654700406725750247719922180221196573 | None | ||
| xbar_stress_all_with_reset_error | 27885000614255107168085721282391762820359782745172454120145545844913621272382 | None | ||
| chip_sw_all_escalation_resets | 14108981158069018921641236539578174170596087179969265410814176744984340684739 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 33809168006698337111379891420678985236827869696875133208613376589031641540939 | None | ||
| xbar_smoke | 114763993834770844478312156964535595906494536824979811011303403103969477502713 | None | ||
| xbar_smoke_zero_delays | 33399317880354489262804876322335203752761114750311669108366992132658195029276 | None | ||
| xbar_smoke_large_delays | 42855813974599153758331435697502316123601379660071117799477677665970491561501 | None | ||
| xbar_smoke_slow_rsp | 2970382578643369035261034491081747172746105238507481082795469912776257386648 | None | ||
| xbar_random | 22782288971720965659719775708432797487410238342554770173705189724347854298025 | None | ||
| xbar_random_zero_delays | 14501390076358980336909012837102126997331957821326969894620762987354338295672 | None | ||
| xbar_random_large_delays | 114908084904922998947306467926378080342974323565817850351692104278924091255136 | None | ||
| xbar_random_slow_rsp | 60596356371349267730151329893651905053754517930176386129527507633779409876767 | None | ||
| xbar_access_same_device | 80391875512653935742207691375875728992566553501940972605276588512200920989842 | None | ||
| xbar_access_same_device_slow_rsp | 43555399354924616078182155444009921110191454202887976435440282987127147663322 | None | ||
| xbar_same_source | 113913785129224958288588461861435145599926550481628041296312326572185598051589 | None | ||
| xbar_error_random | 64772944629858201566105202164420768122733905883328826139856684532846113454697 | None | ||
| xbar_unmapped_addr | 86638670754047576997001494474688117468055906786091178602420765510848579230742 | None | ||
| xbar_error_and_unmapped_addr | 52733341032407296156230969409034458703996952091782369741415472570691431721310 | None | ||
| xbar_stress_all | 101961014045117141448626777013180221122711595159010696852500474477277082022587 | None | ||
| xbar_stress_all_with_rand_reset | 82007461121481722574243945711879648050079578447488114156922390267604854727675 | None | ||
| xbar_stress_all_with_error | 41357927931962475610083137273350564577569073200351788206621742914681242838541 | None | ||
| xbar_stress_all_with_reset_error | 28780696005486209081869461660760634151862194815642158155314884759724984258916 | None | ||
| chip_sw_all_escalation_resets | 530358792962273942111926083512759119055409015296109458599477637163111604299 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 87597707467647086424169919333799764675670728033227058952245621987433577584559 | None | ||
| chip_sw_all_escalation_resets | 42333821665480461331380424602768409625382449921700295525244269934376951915688 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 93636678520863872313200444057714398405981441493299314934188143247569554852579 | None | ||
| chip_sw_all_escalation_resets | 28816674921971852393785934747943982078805870914298260466156780053782453615555 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 100670954254815050277763053944493456797652128685552366495269929615025394341285 | None | ||
| chip_sw_all_escalation_resets | 11379469952886709884419102966040896708718446608434861044247306242495293329277 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 80709381100954100680346348460677837263545187755265125412131299209605432118759 | None | ||
| chip_sw_all_escalation_resets | 79082801331548651850925782845973469387383386581429762063871492189735026983307 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 24951620764926602449186899624487855237744256236814646683365651045779580813192 | None | ||
| chip_sw_all_escalation_resets | 21061001618982384698986468981438952765479170681697445047817810932421952958670 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 60692168961356278996524017820910275339908603153376760138889349109946553713383 | None | ||
| chip_sw_all_escalation_resets | 88055347694903182683488961302995211440189194284255083071038521939435229949606 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 93419404522827469101426334961283519265329990021919756425930259254830324248009 | None | ||
| chip_sw_all_escalation_resets | 28241167415545080984655981445742520110214067679537550335060258705903560382847 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 78964453212449536334161998309756594054548652022025691283707520558995886843058 | None | ||
| chip_sw_all_escalation_resets | 51306839868961679792389963238446528195703077225997226916710146692560324266703 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 101529462375294395859580151930083257387490796929110501815270231432574279115755 | None | ||
| chip_sw_all_escalation_resets | 110599120200551639647595273854240906101761210021198244389934903295271478729769 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 29486588260158019130699121782930744828376090203175290658344348420776282943609 | None | ||
| chip_sw_all_escalation_resets | 63505477349347982836487084244559417808440099513349490427677100119653075278481 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 107446072135836233620454826743752758894014072728994275808802224924518962089682 | None | ||
| chip_sw_all_escalation_resets | 35139658650465356865029570811101914308046324990649379561972324839569551436328 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 50748174953977968172028573494820473115151761445076686543847274306433292564273 | None | ||
| chip_sw_all_escalation_resets | 21834795837120958243742452632524976337593952684707734738854532052283569276515 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 24323406724363223008554896542940405668580409485937179349151035114420564268919 | None | ||
| chip_sw_all_escalation_resets | 91719195546852488554698710043311110189286451419755846345377053285322668544371 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 4299224729651424798541910983018063228680696470485559753839983647809493532449 | None | ||
| chip_sw_all_escalation_resets | 78558897025881343645372093372068403749524755612541026910552973879454045591903 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 56268800048574261863073877697266599412263129968790991262532692313773644746822 | None | ||
| chip_sw_all_escalation_resets | 44669084590840360163555766507395544901485642598004163866245117820837852595379 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 104371466043030284978878286011171773887734218451752516120706096808455910255907 | None | ||
| chip_sw_all_escalation_resets | 106977247193519155669549314280821451391381264959238784191357104472111195155079 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 64486950852082556866678880392476641388581805672591820582097832505840690106438 | None | ||
| chip_sw_all_escalation_resets | 31478135130970420371521697274964150956997579249001695687902876327746780155815 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 91940799008387000819614154260815892225158588153914469187179041835843124680982 | None | ||
| chip_sw_all_escalation_resets | 69484616907221240674583369263349498148179069685415447059916759290067191499180 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 1133465328061476068884894377000452154557734808863330669581133595980617742102 | None | ||
| chip_sw_all_escalation_resets | 75348448893294838032738786913171131209515409772847736168293961079337284709866 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 63153291151053454905167005464612006172955334049354576636133285328240288723253 | None | ||
| chip_sw_all_escalation_resets | 59199580447296545118887967561377060714052422070735482613481692131494878077070 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 78190047987767181700100089626503333977193010883211088496165221072818415946431 | None | ||
| chip_sw_all_escalation_resets | 84394506299797256134805991277156424347411144185994389261313684681172649547559 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 22359447701135226627799207565617576184595039010082966484608331172743236670951 | None | ||
| chip_sw_all_escalation_resets | 67636164536686510001481616557893001464404191450620926412552890890855221207873 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 9829569064490267704969709078648863189979305900285312039695820228776590957607 | None | ||
| chip_sw_all_escalation_resets | 77114364648995079496228213906694366440871402378645071962759503170115620465317 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 87669635336352154698873869607748935031440740926268942098427853072388078237870 | None | ||
| chip_sw_all_escalation_resets | 57073266815669947330703586204321936810828277484966835521059335025475125170861 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 36193416766084577358521883121159515599650676644731005278274284446446254527551 | None | ||
| chip_sw_all_escalation_resets | 85054341195639263272163955887687659582003724293252080005204956645982845699739 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 75603927745966484233917239819373418428330126903863578837771895723320644355723 | None | ||
| chip_sw_all_escalation_resets | 7036786612480146847992989583247730964318422441101214319840176557905837136585 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 125693914023381182411270258388834255192829632981906566052356456561456229455 | None | ||
| chip_sw_all_escalation_resets | 63261482282958858453750180863348150707761200342037000141048101985374300942399 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 113558144737314689217015725236028333593703487565251456650912946686325752792496 | None | ||
| chip_sw_all_escalation_resets | 55469902260466347727698659520393911133392955507046762815465231503385211789445 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 96038029560758777015166435166044316714658209291597142921904172336479115722080 | None | ||
| chip_sw_all_escalation_resets | 41293389411654219287548746046988715676878266660735203763149731592067110784683 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 102454813089062067425153455416718698260951876072996665945434179080885009412695 | None | ||
| chip_sw_all_escalation_resets | 70345136256972257400279115151186933325131492474532028082649129846865366053742 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 56857310059876452668798054667736505700639467968847651264727192268035796810310 | None | ||
| chip_sw_all_escalation_resets | 52307630482680709307158455083658748618837548707646329333315843299874524268879 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 7814770502985528105470521690448183194436139715477461544829175127169220647086 | None | ||
| chip_sw_all_escalation_resets | 51130098323810923026495152703013456455981709523427660864321981572860485809455 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 99559296434889640256329878284926551559482578946102962840014359454297226363584 | None | ||
| chip_sw_all_escalation_resets | 115014398821502271941780777553766646591837226271067387532080157898040800804866 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 87540594158461933821099312425038809646769671981059052687083439539577887092009 | None | ||
| chip_sw_all_escalation_resets | 106654846914028775178104414756730694729231508645173571989088089450828589705301 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 55156929073029018127115621196572736648021622734653160226315607432122307509444 | None | ||
| chip_sw_all_escalation_resets | 104420984943179021921173314725044288529966482994279735251927294787319220738781 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 92776620451881349867162138392087677145320343646911622525172122652364497575185 | None | ||
| chip_sw_all_escalation_resets | 74773536130224376131783005889863026337651994578226336800790464803939510938679 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 6248014873325152883632867928502334264056252460834492471779720060474692451550 | None | ||
| chip_sw_all_escalation_resets | 24231937188027078641509009441551166086644106851245266509165728585601319768800 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 37318249411268755539088929452657812430689556239081000681228669832849620604775 | None | ||
| chip_sw_all_escalation_resets | 59246107461235587671268561687019671100006895468577697548279457044445531697925 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 47624682062840310931522077562880744640731795918857683617988709384206361409343 | None | ||
| chip_sw_all_escalation_resets | 21105342705260027520669763308949716184419181111878833184914025212572115079058 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 88841287067899090506361279022037159944428782127024242511965357723640606941955 | None | ||
| chip_sw_all_escalation_resets | 8625091858946203691546759671331120453140799138700218201626262701736138752616 | None | ||
| chip_sw_all_escalation_resets | 6348851687907699344356088140446303145924335418715520563644210916919749721836 | None | ||
| chip_sw_all_escalation_resets | 85048352177331381747335812881315651620878478223901220707309941925171524785513 | None | ||
| chip_sw_all_escalation_resets | 9196996950043721836595293933239432752193021071860589971331422835326165440506 | None | ||
| chip_sw_all_escalation_resets | 38571915054111604195040606829761491009575693812602421138876887042283962688513 | None | ||
| chip_sw_all_escalation_resets | 10175728116707990411170295352517128979202344073304389835174506055760987623858 | None | ||
| chip_sw_all_escalation_resets | 12698323275491671572354502362358949132416515990960386356487490456947764595899 | None | ||
| chip_sw_all_escalation_resets | 38443012582442951160654115483021895394402356237030133639888811308553342653580 | None | ||
| chip_sw_all_escalation_resets | 57990135803719300006255507112146897306871310661555555159411285536181050008059 | None | ||
| chip_sw_all_escalation_resets | 35415092780807216590685278046335769132846501620910223664054603408438331670162 | None | ||
| chip | None | None | ||
| Error-[SE] Syntax error | 4 test runs | |||
| cover_reg_top | None | 3031 |
Following verilog source has syntax error :
Select on function call
"src/lowrisc_dv_rram_ctrl_bkdr_util_0.1/rram_ctrl_otp_bkdr_util.sv", 149:
token is ']'
|
|
| default | None | 3033 |
Following verilog source has syntax error :
Select on function call
"src/lowrisc_dv_rram_ctrl_bkdr_util_0.1/rram_ctrl_otp_bkdr_util.sv", 149:
token is ']'
|
|
| pad_ctrl_test_mode | None | 3031 |
Following verilog source has syntax error :
Select on function call
"src/lowrisc_dv_rram_ctrl_bkdr_util_0.1/rram_ctrl_otp_bkdr_util.sv", 149:
token is ']'
|
|
| xbar_build_mode | None | 3033 |
Following verilog source has syntax error :
Select on function call
"src/lowrisc_dv_rram_ctrl_bkdr_util_0.1/rram_ctrl_otp_bkdr_util.sv", 149:
token is ']'
|
|
| Job cancelled because all of its dependencies failed or were killed. | 1 test run | |||
| chip | None | None | ||