Simulation Results

Simulation Results: clkmgr

15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
93.88 %

code
98.57 %

assert
95.76 %

func
87.31 %

line
99.07 %

branch
98.74 %

cond
95.85 %

toggle
99.19 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		81.38%
V3		100.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	1.320s	85.018us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.190s	45.517us	1	1	100.00
csr_rw				5	5	100.00
	clkmgr_csr_rw	1.230s	23.577us	5	5	100.00
csr_bit_bash				1	1	100.00
	clkmgr_csr_bit_bash	8.580s	597.661us	1	1	100.00
csr_aliasing				1	1	100.00
	clkmgr_csr_aliasing	1.940s	29.083us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	clkmgr_csr_mem_rw_with_rand_reset	2.580s	315.280us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	clkmgr_csr_rw	1.230s	23.577us	5	5	100.00
	clkmgr_csr_aliasing	1.940s	29.083us	1	1	100.00

127/127 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	1.550s	124.370us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	1.560s	75.997us	10	10	100.00
extclk				10	10	100.00
	clkmgr_extclk	1.510s	129.185us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	1.250s	78.987us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	1.320s	85.018us	10	10	100.00
frequency				10	10	100.00
	clkmgr_frequency	13.520s	2550.165us	10	10	100.00
frequency_timeout				10	10	100.00
	clkmgr_frequency_timeout	13.710s	1576.044us	10	10	100.00
frequency_overflow				10	10	100.00
	clkmgr_frequency	13.520s	2550.165us	10	10	100.00
stress_all				10	10	100.00
	clkmgr_stress_all	66.530s	12708.145us	10	10	100.00
alert_test				10	10	100.00
	clkmgr_alert_test	2.080s	271.903us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	5.720s	620.471us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	5.720s	620.471us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	clkmgr_csr_hw_reset	1.190s	45.517us	1	1	100.00
	clkmgr_csr_rw	1.230s	23.577us	5	5	100.00
	clkmgr_csr_aliasing	1.940s	29.083us	1	1	100.00
	clkmgr_same_csr_outstanding	2.320s	199.597us	5	5	100.00
tl_d_partial_access				12	12	100.00
	clkmgr_csr_hw_reset	1.190s	45.517us	1	1	100.00
	clkmgr_csr_rw	1.230s	23.577us	5	5	100.00
	clkmgr_csr_aliasing	1.940s	29.083us	1	1	100.00
	clkmgr_same_csr_outstanding	2.320s	199.597us	5	5	100.00

V2S

118/145 passed

81.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				14	30	46.67
	clkmgr_sec_cm	43.860s	10052.773us	0	5	0.00
	clkmgr_tl_intg_err	79.080s	10033.443us	14	25	56.00
shadow_reg_update_error				16	20	80.00
	clkmgr_shadow_reg_errors	987.810s	200000.000us	16	20	80.00
shadow_reg_read_clear_staged_value				16	20	80.00
	clkmgr_shadow_reg_errors	987.810s	200000.000us	16	20	80.00
shadow_reg_storage_error				16	20	80.00
	clkmgr_shadow_reg_errors	987.810s	200000.000us	16	20	80.00
shadowed_reset_glitch				16	20	80.00
	clkmgr_shadow_reg_errors	987.810s	200000.000us	16	20	80.00
shadow_reg_update_error_with_csr_rw				14	20	70.00
	clkmgr_shadow_reg_errors_with_csr_rw	941.050s	200000.000us	14	20	70.00
sec_cm_bus_integrity				14	25	56.00
	clkmgr_tl_intg_err	79.080s	10033.443us	14	25	56.00
sec_cm_meas_clk_bkgn_chk				10	10	100.00
	clkmgr_frequency	13.520s	2550.165us	10	10	100.00
sec_cm_timeout_clk_bkgn_chk				10	10	100.00
	clkmgr_frequency_timeout	13.710s	1576.044us	10	10	100.00
sec_cm_meas_config_shadow				16	20	80.00
	clkmgr_shadow_reg_errors	987.810s	200000.000us	16	20	80.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	1.870s	159.160us	10	10	100.00
sec_cm_lc_ctrl_intersig_mubi				10	10	100.00
	clkmgr_lc_ctrl_intersig_mubi	1.480s	92.213us	10	10	100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi				10	10	100.00
	clkmgr_lc_clk_byp_req_intersig_mubi	1.630s	133.617us	10	10	100.00
sec_cm_clk_handshake_intersig_mubi				9	10	90.00
	clkmgr_clk_handshake_intersig_mubi	1.410s	68.733us	9	10	90.00
sec_cm_div_intersig_mubi				10	10	100.00
	clkmgr_div_intersig_mubi	1.570s	100.980us	10	10	100.00
sec_cm_jitter_config_mubi				5	5	100.00
	clkmgr_csr_rw	1.230s	23.577us	5	5	100.00
sec_cm_idle_ctr_redun				0	5	0.00
	clkmgr_sec_cm	43.860s	10052.773us	0	5	0.00
sec_cm_meas_config_regwen				5	5	100.00
	clkmgr_csr_rw	1.230s	23.577us	5	5	100.00
sec_cm_clk_ctrl_config_regwen				5	5	100.00
	clkmgr_csr_rw	1.230s	23.577us	5	5	100.00
prim_count_check				0	5	0.00
	clkmgr_sec_cm	43.860s	10052.773us	0	5	0.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
regwen				10	10	100.00
	clkmgr_regwen	9.290s	1273.524us	10	10	100.00
stress_all_with_rand_reset				10	10	100.00
	clkmgr_stress_all_with_rand_reset	129.570s	22598.851us	10	10	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1087) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault				13 test runs
	clkmgr_tl_intg_err	56804662788403821849467812253033653258938492525303718719539015978091504675821	125	UVM_INFO @ 10066814839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	49964850380628744791843003923061707943477486051189070382270431941565395531351	118	UVM_INFO @ 10052773201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	77858887275581692983587229410383957915852898336036717673892133451562965023993	112	UVM_INFO @ 10099584179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	77617073308110498692042880448184681341656610456613484189643386868313004433910	95	UVM_INFO @ 10013725256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	44580307044595013255704286783227258778055514010975627040028874407139307150686	130	UVM_INFO @ 10033443239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	34179553296626661705804449228014948101619259828509206793748600964220444297825	134	UVM_INFO @ 10047813495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	16034210952304209572507840851147961207665737433360033324936009308077387170897	147	UVM_INFO @ 10084824132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	50675918168266624731934365705375158692425611822295276523098779918630220928353	157	UVM_INFO @ 10176238475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	96471546180354359693119956808880263180894634661402622926387422075686633949308	146	UVM_INFO @ 10050017231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	58988315796037290174983796482357453392876775094267245435053524774509505331662	119	UVM_INFO @ 10137911628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	4046610115316086001002756573615745415343398283098846553431216992604439604824	146	UVM_INFO @ 10200234558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	21927169559505806172470272553475810622190363487742336714346435272101367620086	121	UVM_INFO @ 10017991410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	25229097499733679971677795026758904433035564116763686169869098266346359667920	96	UVM_INFO @ 10010016454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				6 test runs
	clkmgr_shadow_reg_errors	42017593392911463210184045607455389759685998590863512491411660040117695557690	81	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	31720087677226712398696449508074099808426789398330803138642045168298838149556	81	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	54993357010501013784972993967829015073434770737936471419158153213593480001721	81	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	60857831751178310776478290963336293308494613132447465840747424973664897821234	81	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	26495622180759908988380582006208559945944330637074808027232045944072003544079	81	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	102652111775106540445928488834300635730331714671483012795362361652651338853100	81	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				3 test runs
	clkmgr_sec_cm	81685301407132367575106331652484550890090138049764626961337063730208243257560	85	UVM_INFO @ 8998759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	9212124775624020457722132499319122206644920319065536471921724300909726574152	88	UVM_INFO @ 10688582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	5462561448368838901349547379060220994004273965448904756338397537723759503430	117	UVM_INFO @ 65088890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_fault does not trigger!				2 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	74710462920777568538067527460347196575736365074373786644074051357519364983020	81	UVM_INFO @ 30032998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	15966890097877183293542263818472986167747203872001033754973564611701219994251	81	UVM_INFO @ 36425694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [] vs [*]) extclk_status mismatch				1 test run
	clkmgr_clk_handshake_intersig_mubi	57712280174899766067675887824426803260635904360991845130941044740188517460795	80	UVM_INFO @ 7107076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.jitter_regwen (addr=*)				1 test run
	clkmgr_shadow_reg_errors_with_csr_rw	81678575414227367203748348084006336062889881624742421038149209888981964520578	81	UVM_INFO @ 2074073628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.measure_ctrl_regwen (addr=*)				1 test run
	clkmgr_shadow_reg_errors_with_csr_rw	93143143282288735730022463765966636200782728749107314185828479544598407220079	81	UVM_INFO @ 2257562171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---