Simulation Results: csrng

 
15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.82 %
  • code
  • 96.20 %
  • assert
  • 97.16 %
  • func
  • 91.09 %
  • block
  • 98.53 %
  • line
  • 99.54 %
  • branch
  • 96.38 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.39%
V2S
99.07%
V3
10.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 4.000s 222.469us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 28.000s 27.503us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 25.000s 81.333us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 36.000s 251.819us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 34.000s 183.040us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 27.000s 91.463us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 25.000s 81.333us 5 5 100.00
csrng_csr_aliasing 34.000s 183.040us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 30.000s 1919.350us 200 200 100.00
alerts 500 500 100.00
csrng_alert 65.000s 5015.926us 500 500 100.00
err 500 500 100.00
csrng_err 21.000s 33.574us 500 500 100.00
cmds 5 25 20.00
csrng_cmds 151.000s 4773.969us 5 25 20.00
life cycle 5 25 20.00
csrng_cmds 151.000s 4773.969us 5 25 20.00
stress_all 24 25 96.00
csrng_stress_all 1176.000s 77596.579us 24 25 96.00
intr_test 10 10 100.00
csrng_intr_test 5.000s 15.042us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 30.000s 41.757us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 10.000s 241.703us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 10.000s 241.703us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 28.000s 27.503us 1 1 100.00
csrng_csr_rw 25.000s 81.333us 5 5 100.00
csrng_csr_aliasing 34.000s 183.040us 1 1 100.00
csrng_same_csr_outstanding 6.000s 421.348us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 28.000s 27.503us 1 1 100.00
csrng_csr_rw 25.000s 81.333us 5 5 100.00
csrng_csr_aliasing 34.000s 183.040us 1 1 100.00
csrng_same_csr_outstanding 6.000s 421.348us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
csrng_sec_cm 16.000s 330.704us 5 5 100.00
csrng_tl_intg_err 16.000s 1268.786us 25 25 100.00
sec_cm_config_regwen 19 30 63.33
csrng_regwen 3.000s 43.510us 14 25 56.00
csrng_csr_rw 25.000s 81.333us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 65.000s 5015.926us 500 500 100.00
sec_cm_intersig_mubi 24 25 96.00
csrng_stress_all 1176.000s 77596.579us 24 25 96.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 30.000s 1919.350us 200 200 100.00
csrng_err 21.000s 33.574us 500 500 100.00
csrng_sec_cm 16.000s 330.704us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 30.000s 1919.350us 200 200 100.00
csrng_err 21.000s 33.574us 500 500 100.00
csrng_sec_cm 16.000s 330.704us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 30.000s 1919.350us 200 200 100.00
csrng_err 21.000s 33.574us 500 500 100.00
csrng_sec_cm 16.000s 330.704us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 30.000s 1919.350us 200 200 100.00
csrng_err 21.000s 33.574us 500 500 100.00
csrng_sec_cm 16.000s 330.704us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 30.000s 1919.350us 200 200 100.00
csrng_err 21.000s 33.574us 500 500 100.00
csrng_sec_cm 16.000s 330.704us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 65.000s 5015.926us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 30.000s 1919.350us 200 200 100.00
csrng_err 21.000s 33.574us 500 500 100.00
sec_cm_constants_lc_gated 24 25 96.00
csrng_stress_all 1176.000s 77596.579us 24 25 96.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 65.000s 5015.926us 500 500 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
csrng_tl_intg_err 16.000s 1268.786us 25 25 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 30.000s 1919.350us 200 200 100.00
csrng_err 21.000s 33.574us 500 500 100.00
csrng_sec_cm 16.000s 330.704us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 30.000s 1919.350us 200 200 100.00
csrng_err 21.000s 33.574us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 30.000s 1919.350us 200 200 100.00
csrng_err 21.000s 33.574us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 30.000s 1919.350us 200 200 100.00
csrng_err 21.000s 33.574us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 30.000s 1919.350us 200 200 100.00
csrng_err 21.000s 33.574us 500 500 100.00
csrng_sec_cm 16.000s 330.704us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 30.000s 1919.350us 200 200 100.00
csrng_err 21.000s 33.574us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
csrng_stress_all_with_rand_reset 3600.000s 0.000us 1 10 10.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:667) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 19 test runs
csrng_cmds 96155713867283834996651525418402139808002798163301115278263137855423115577392 100
UVM_INFO @ 83460209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 83968516409266362049517991096805677043989810868974608649035632427892764007541 100
UVM_INFO @ 280227200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 101461239318074084838105900443598730648953329990883847780048261387324626569852 100
UVM_INFO @ 62864929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 83906942798116631381528022095281501182592504798585735235035385948732656054213 100
UVM_INFO @ 156647253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 32325087658319822567856218017470152833803122210219946276272415874655569731345 100
UVM_INFO @ 7008548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 111201922034580165804733008026482211476885240525594207679540090969356544641944 100
UVM_INFO @ 95649993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 71492140977360207688755326605744897713852666337365357327224180347445130854741 100
UVM_INFO @ 148845603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 32663885441580109409133884338921375700599576564063811039251958129476338565565 110
UVM_INFO @ 106585718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 56118214689207108642672758036041245735896446603956249188324690981083708696684 100
UVM_INFO @ 234050226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 98561547166923458576078925028485913781313255017423740218577757575290302526489 110
UVM_INFO @ 97019704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 8743045706292039630983802124985198351236541300591878586578113995272605590010 109
UVM_INFO @ 313486796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 14316213364427083278056830660543854755985612704132217025887009255216152138697 100
UVM_INFO @ 14433491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 38985854532267355914606391436404839634779857639737310317098512425199966090290 110
UVM_INFO @ 474336634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 50613422485550897709582712089046207285015463317781297797063926860387151447427 100
UVM_INFO @ 108989302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 57571502241898048099071927891820970194117663702130716034164428726144425354283 100
UVM_INFO @ 164310331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 54364584776758756061696182675157692051081441658970282146103449622510018394905 100
UVM_INFO @ 177168568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 87086258008740224542245060023713022076518226777218472960506788666179077892610 100
UVM_INFO @ 228547885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 68274406238749692897279216466291125515087416844678559519850605378060702687913 100
UVM_INFO @ 68490251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 86163865588023649250985071789583652475146539890650391510942215159909968230494 100
UVM_INFO @ 884989944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 9 test runs
csrng_regwen 67760246221187152918717038959713498129825571355359694755912556478191978030518 99
UVM_INFO @ 4277605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 23958989680392617270945429067725395510506651293633474246338944506760726175947 99
UVM_INFO @ 2983263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 16543944361533561839947507395220358378159720797290162940362941632538368978455 99
UVM_INFO @ 5769989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 75465903867582328223445977737439110986604273909992022470202601166094406226588 99
UVM_INFO @ 3362296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 61063208185884484028588190066987081370969650797456766484270585287946521717118 99
UVM_INFO @ 5646991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 66259221905835565009174941596226640083404050293185462126936199015792322089988 99
UVM_INFO @ 1517924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 18501495820209873516987309706317240217212461720625487432034736753719116024435 99
UVM_INFO @ 14474633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 110269903058327281092815210560076014973444179430270880783235957946143609555190 99
UVM_INFO @ 2626468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 27990310883673471428056586544993258624016221243514856785492167190208766152140 99
UVM_INFO @ 17796839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 7 test runs
csrng_stress_all_with_rand_reset 43590269718077200935761067027876547877802729384266271622669521818304174550811 None
csrng_stress_all_with_rand_reset 3002478452472846816835666512133162952085206931544096013638964644402182285126 None
csrng_stress_all_with_rand_reset 58064003634454261561214815128163771550925445664613229696190461461409101889389 None
csrng_stress_all_with_rand_reset 14931347279021849979356584355630859314256758156220127299730243912538541778749 None
csrng_stress_all_with_rand_reset 58118725140806860921543605299649626693946922397518765532501001592661658571550 None
csrng_stress_all_with_rand_reset 29621495710156561863018252986762430375968482190592983873591637049709128831417 None
csrng_stress_all_with_rand_reset 102708951623662646612108127533710865283237374238811514898159977184930795850456 None
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 2 test runs
csrng_regwen 64996580677659388774187425595542467141599906937782372242668809602921630955026 99
UVM_INFO @ 12536180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 53172711779835303691324064624057188942956634343840341784267851171720186841407 99
UVM_INFO @ 8884322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:173) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 2 test runs
csrng_stress_all_with_rand_reset 109255716591276547684086912743452618864195339662430689410210029812751926981594 136
UVM_INFO @ 1163350793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 91854111420083293009916131663337757741165261226399864307362684080363502977408 106
UVM_INFO @ 26320316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 1 test run
csrng_stress_all_with_rand_reset 65226451064072949268593344574457577071980781131202816478515508213056096773181 134
UVM_INFO @ 639250650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly 1 test run
csrng_cmds 23337708760186466664545632979272721268896142079050437742215784020287973823583 108
UVM_INFO @ 9280099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---