Simulation Results: edn/edn0

 
15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.38 %
  • code
  • 95.47 %
  • assert
  • 97.61 %
  • func
  • 93.06 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 93.96 %
  • toggle
  • 97.12 %
  • FSM
  • 90.86 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.390s 19.303us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.270s 63.324us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.180s 13.166us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.480s 226.726us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.480s 27.141us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.590s 40.112us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.180s 13.166us 5 5 100.00
edn_csr_aliasing 1.480s 27.141us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 4.020s 252.856us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 4.020s 252.856us 100 100 100.00
genbits 100 100 100.00
edn_genbits 4.020s 252.856us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.610s 22.798us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.890s 386.092us 200 200 100.00
errs 100 100 100.00
edn_err 1.630s 44.254us 100 100 100.00
disable 95 100 95.00
edn_disable 1.340s 13.769us 50 50 100.00
edn_disable_auto_req_mode 14.030s 500.000us 45 50 90.00
stress_all 30 30 100.00
edn_stress_all 8.720s 404.178us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.190s 37.506us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.340s 54.209us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 4.160s 423.494us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 4.160s 423.494us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.270s 63.324us 1 1 100.00
edn_csr_rw 1.180s 13.166us 5 5 100.00
edn_csr_aliasing 1.480s 27.141us 1 1 100.00
edn_same_csr_outstanding 1.610s 319.131us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.270s 63.324us 1 1 100.00
edn_csr_rw 1.180s 13.166us 5 5 100.00
edn_csr_aliasing 1.480s 27.141us 1 1 100.00
edn_same_csr_outstanding 1.610s 319.131us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 7.520s 1028.049us 5 5 100.00
edn_tl_intg_err 3.150s 1145.021us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.370s 18.370us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.890s 386.092us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.520s 1028.049us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.520s 1028.049us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.520s 1028.049us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.520s 1028.049us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.890s 386.092us 200 200 100.00
edn_sec_cm 7.520s 1028.049us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.890s 386.092us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.150s 1145.021us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 24 30 80.00
edn_stress_all_with_rand_reset 147.160s 12438.345us 24 30 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
edn_stress_all_with_rand_reset 101302906847048502818084287369729835222420736799468841849984864970383441570473 239
UVM_INFO @ 1004301801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 31598401054566227860116056604649931079726232498351959032265758631405202159168 279
UVM_INFO @ 1418447343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 59296760708359258292687079127250240495722195168563911856538482112052990841365 194
UVM_INFO @ 584930021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 98138834425189573732304555411180370532696879535784003937635947078078219046935 185
UVM_INFO @ 891739055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 3 test runs
edn_disable_auto_req_mode 37326840531157514811176147958834255735164424013945873028384821486565918952212 94
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 17390863382029576834127812783453166415626725159439298701419833497630789461149 95
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 105708130009159656456671836513421358858932877610720701469968034424889903648922 94
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:425) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 2 test runs
edn_disable_auto_req_mode 8693476725303483889688218060420468397781575431688028697328730083669172483138 94
UVM_INFO @ 67669715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 19077557988960136221105063988992329382295672191049600475903070377264660321322 94
UVM_INFO @ 98494878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 9001077414899182133882036991475683390603435818255054157101597628072762139913 259
UVM_INFO @ 12438345248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit 1 test run
edn_stress_all_with_rand_reset 42651544350410402617677807745062985397138196387461127826089663518121051639473 208
/nightly/current_run/scratch/master/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 2345919168 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup