Simulation Results: edn/edn1

 
15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.60 %
  • code
  • 96.18 %
  • assert
  • 98.18 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.08 %
  • toggle
  • 96.15 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
76.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.270s 34.629us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 38.610us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.130s 16.415us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.360s 622.580us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.620s 76.629us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.730s 112.222us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.130s 16.415us 5 5 100.00
edn_csr_aliasing 1.620s 76.629us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 8.470s 1334.120us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 8.470s 1334.120us 100 100 100.00
genbits 100 100 100.00
edn_genbits 8.470s 1334.120us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.540s 23.310us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.700s 310.395us 200 200 100.00
errs 100 100 100.00
edn_err 1.550s 60.728us 100 100 100.00
disable 95 100 95.00
edn_disable 1.270s 14.268us 50 50 100.00
edn_disable_auto_req_mode 8.330s 500.000us 45 50 90.00
stress_all 30 30 100.00
edn_stress_all 5.780s 528.184us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.120s 42.889us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.240s 19.517us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.750s 289.758us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.750s 289.758us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 0.810s 38.610us 1 1 100.00
edn_csr_rw 1.130s 16.415us 5 5 100.00
edn_csr_aliasing 1.620s 76.629us 1 1 100.00
edn_same_csr_outstanding 1.360s 25.221us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 0.810s 38.610us 1 1 100.00
edn_csr_rw 1.130s 16.415us 5 5 100.00
edn_csr_aliasing 1.620s 76.629us 1 1 100.00
edn_same_csr_outstanding 1.360s 25.221us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 5.190s 335.863us 5 5 100.00
edn_tl_intg_err 3.940s 228.604us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.250s 18.665us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.700s 310.395us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.190s 335.863us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.190s 335.863us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 5.190s 335.863us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 5.190s 335.863us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.700s 310.395us 200 200 100.00
edn_sec_cm 5.190s 335.863us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.700s 310.395us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.940s 228.604us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 23 30 76.67
edn_stress_all_with_rand_reset 114.370s 19352.379us 23 30 76.67

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
edn_stress_all_with_rand_reset 92487195776705309504977077143078728128976872993331035273054714778912812753927 269
UVM_INFO @ 2849265886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 20410304832975385193484141949148900273911945520268513032369088868866763926768 168
UVM_INFO @ 1106444809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 38357578114565496302394130021455447881317119890661895742999142377849444413197 217
UVM_INFO @ 1697431906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 60851239239492804767984347568772354170721556447992735685864183437254818863427 183
UVM_INFO @ 1128088751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 104703617240786699517288617630578244217802529860897689227414205209931719436387 201
UVM_INFO @ 1658251365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 85258883032077793662389698821051186790486317131736673823525060405249524971374 167
UVM_INFO @ 148498141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
edn_disable_auto_req_mode 105871282091352730963284109376781851633515001433245838233584191590785018280854 94
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 32399995893010349918683961873648299711902867779551942148844283018762059405631 96
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 66749894637143429834720452528248881007323787492408667605191304385013232566022 94
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 86554636251064186178084379167019354989584881324396505890254669933200840751859 94
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 44492820360236796872830030698609551217978200673676328212990601856068724927185 141
UVM_INFO @ 10027508569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:425) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 94589121872231607353831825809443312754879128083805804477208283314754083944405 94
UVM_INFO @ 22071053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---