Simulation Results

Simulation Results: flash_ctrl

15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.93 %

code
95.39 %

assert
96.94 %

func
98.45 %

line
96.11 %

branch
97.47 %

cond
94.92 %

toggle
96.60 %

FSM
91.84 %

Validation stages

V1		100.00%
V2		98.07%
V2S		98.32%
V3		100.00%
unmapped		100.00%

70/70 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	153.680s	39.097us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	24.630s	19.705us	5	5	100.00
csr_hw_reset				1	1	100.00
	flash_ctrl_csr_hw_reset	29.860s	50.993us	1	1	100.00
csr_rw				5	5	100.00
	flash_ctrl_csr_rw	19.150s	29.093us	5	5	100.00
csr_bit_bash				1	1	100.00
	flash_ctrl_csr_bit_bash	67.740s	33163.879us	1	1	100.00
csr_aliasing				1	1	100.00
	flash_ctrl_csr_aliasing	27.910s	218.982us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	flash_ctrl_csr_mem_rw_with_rand_reset	19.350s	101.786us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	flash_ctrl_csr_rw	19.150s	29.093us	5	5	100.00
	flash_ctrl_csr_aliasing	27.910s	218.982us	1	1	100.00
mem_walk				1	1	100.00
	flash_ctrl_mem_walk	6.330s	18.188us	1	1	100.00
mem_partial_access				1	1	100.00
	flash_ctrl_mem_partial_access	10.260s	18.366us	1	1	100.00

917/935 passed

98.07 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	26.340s	55.143us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	67.120s	92.452us	5	5	100.00
rma_hw_if				42	43	97.67
	flash_ctrl_hw_rma	1349.150s	334708.482us	2	3	66.67
	flash_ctrl_hw_rma_reset	804.340s	160184.361us	20	20	100.00
	flash_ctrl_lcmgr_intg	14.930s	24.432us	20	20	100.00
host_controller_arb				5	5	100.00
	flash_ctrl_host_ctrl_arb	1478.990s	369649.577us	5	5	100.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	308.500s	10406.262us	5	5	100.00
program_reset				30	30	100.00
	flash_ctrl_prog_reset	138.760s	5110.773us	30	30	100.00
full_memory_access				0	5	0.00
	flash_ctrl_full_mem_access	2901.970s	206283.059us	0	5	0.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	93.530s	1006.052us	5	5	100.00
rd_buff_eviction_w_ecc				102	105	97.14
	flash_ctrl_rw_evict	34.670s	32.559us	37	40	92.50
	flash_ctrl_rw_evict_all_en	34.080s	47.459us	40	40	100.00
	flash_ctrl_re_evict	34.610s	73.916us	25	25	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	232.870s	2877.307us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	232.870s	2877.307us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	309.920s	6884.475us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	28.500s	4879.091us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	815.840s	1071.199us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	720.770s	85832.974us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	568.070s	931.990us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1570.320s	760.023us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	14.410s	22.979us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	154.500s	9353.484us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	24.950s	30.079us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	18.780s	17.072us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	678.110s	774.181us	5	5	100.00
secret_partition				129	130	99.23
	flash_ctrl_hw_sec_otp	168.120s	13435.282us	50	50	100.00
	flash_ctrl_otp_reset	115.490s	39.302us	79	80	98.75
isolation_partition				2	3	66.67
	flash_ctrl_hw_rma	1349.150s	334708.482us	2	3	66.67
interrupts				98	100	98.00
	flash_ctrl_intr_rd	185.400s	13860.795us	38	40	95.00
	flash_ctrl_intr_wr	79.990s	5856.546us	10	10	100.00
	flash_ctrl_intr_rd_slow_flash	345.670s	46596.838us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	196.500s	21539.899us	10	10	100.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	73.330s	8730.248us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	53.600s	1091.268us	5	5	100.00
double_bit_err				33	35	94.29
	flash_ctrl_read_word_sweep_derr	24.620s	111.431us	5	5	100.00
	flash_ctrl_ro_derr	111.550s	5135.544us	10	10	100.00
	flash_ctrl_rw_derr	160.900s	10477.965us	10	10	100.00
	flash_ctrl_derr_detect	141.680s	6465.174us	5	5	100.00
	flash_ctrl_integrity	2969.370s	200000.000us	3	5	60.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	21.170s	58.365us	5	5	100.00
	flash_ctrl_ro_serr	101.320s	1812.131us	10	10	100.00
	flash_ctrl_rw_serr	170.210s	15594.473us	10	10	100.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	55.250s	3128.919us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	68.290s	1164.584us	5	5	100.00
scramble				58	62	93.55
	flash_ctrl_wo	153.850s	3174.575us	20	20	100.00
	flash_ctrl_write_word_sweep	7.930s	84.795us	1	1	100.00
	flash_ctrl_read_word_sweep	13.440s	57.176us	1	1	100.00
	flash_ctrl_ro	100.520s	3095.399us	20	20	100.00
	flash_ctrl_rw	3604.015s	0.000us	16	20	80.00
filesystem_support				5	5	100.00
	flash_ctrl_fs_sup	29.650s	2167.916us	5	5	100.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	688.780s	40803.350us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	223.390s	10020.468us	20	20	100.00
alert_test				10	10	100.00
	flash_ctrl_alert_test	14.940s	62.992us	10	10	100.00
intr_test				10	10	100.00
	flash_ctrl_intr_test	14.400s	42.108us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	flash_ctrl_tl_errors	20.160s	197.846us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	flash_ctrl_tl_errors	20.160s	197.846us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	flash_ctrl_csr_hw_reset	29.860s	50.993us	1	1	100.00
	flash_ctrl_csr_rw	19.150s	29.093us	5	5	100.00
	flash_ctrl_csr_aliasing	27.910s	218.982us	1	1	100.00
	flash_ctrl_same_csr_outstanding	31.800s	143.191us	5	5	100.00
tl_d_partial_access				12	12	100.00
	flash_ctrl_csr_hw_reset	29.860s	50.993us	1	1	100.00
	flash_ctrl_csr_rw	19.150s	29.093us	5	5	100.00
	flash_ctrl_csr_aliasing	27.910s	218.982us	1	1	100.00
	flash_ctrl_same_csr_outstanding	31.800s	143.191us	5	5	100.00

V2S

467/475 passed

98.32 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	87.490s	180.039us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	87.490s	180.039us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	87.490s	180.039us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	87.490s	180.039us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	76.370s	102.419us	20	20	100.00
tl_intg_err				30	30	100.00
	flash_ctrl_sec_cm	2389.390s	1778.235us	5	5	100.00
	flash_ctrl_tl_intg_err	622.360s	9198.906us	25	25	100.00
sec_cm_reg_bus_integrity				25	25	100.00
	flash_ctrl_tl_intg_err	622.360s	9198.906us	25	25	100.00
sec_cm_host_bus_integrity				25	25	100.00
	flash_ctrl_tl_intg_err	622.360s	9198.906us	25	25	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	27.380s	79.513us	3	3	100.00
	flash_ctrl_wr_intg	14.330s	53.031us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	153.680s	39.097us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				259	260	99.62
	flash_ctrl_otp_reset	115.490s	39.302us	79	80	98.75
	flash_ctrl_disable	24.950s	30.079us	50	50	100.00
	flash_ctrl_sec_info_access	83.300s	10821.888us	50	50	100.00
	flash_ctrl_connect	18.780s	17.072us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	13.650s	56.752us	5	5	100.00
sec_cm_data_regions_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	19.150s	29.093us	5	5	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	87.490s	180.039us	20	20	100.00
sec_cm_info_regions_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	19.150s	29.093us	5	5	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	87.490s	180.039us	20	20	100.00
sec_cm_bank_config_regwen				5	5	100.00
	flash_ctrl_csr_rw	19.150s	29.093us	5	5	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	87.490s	180.039us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	24.950s	30.079us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	27.380s	79.513us	3	3	100.00
	flash_ctrl_access_after_disable	14.600s	23.096us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	26.970s	35.531us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	24.950s	30.079us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	28.500s	4879.091us	10	10	100.00
sec_cm_mem_scramble				16	20	80.00
	flash_ctrl_rw	3604.015s	0.000us	16	20	80.00
sec_cm_mem_integrity				23	25	92.00
	flash_ctrl_rw_serr	170.210s	15594.473us	10	10	100.00
	flash_ctrl_rw_derr	160.900s	10477.965us	10	10	100.00
	flash_ctrl_integrity	2969.370s	200000.000us	3	5	60.00
sec_cm_rma_entry_mem_sec_wipe				2	3	66.67
	flash_ctrl_hw_rma	1349.150s	334708.482us	2	3	66.67
sec_cm_ctrl_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2389.390s	1778.235us	5	5	100.00
sec_cm_phy_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2389.390s	1778.235us	5	5	100.00
sec_cm_phy_prog_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2389.390s	1778.235us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2389.390s	1778.235us	5	5	100.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	17.630s	880.661us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_host_grant_err	14.920s	41.260us	5	5	100.00
sec_cm_phy_ack_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_ack_consistency	14.720s	56.322us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2389.390s	1778.235us	5	5	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2389.390s	1778.235us	5	5	100.00
sec_cm_prog_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2389.390s	1778.235us	5	5	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	23.440s	131.337us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	367.930s	316.666us	3	3	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (flash_ctrl_scoreboard.sv:735) [scoreboard] Check failed exp_data_part[addr] == data (* [] vs []) read addr: data: *				5 test runs
	flash_ctrl_full_mem_access	63917194998132731873421474207504651084985178649638270189501595965618091006774	275581	UVM_INFO @ 206283059.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_full_mem_access	94165562818307467354784781929142676614171441359180398290986344853836423914340	275581	UVM_INFO @ 597829078.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_full_mem_access	42864485697852551432970228501563049528356147714059076725601194637157314460421	275581	UVM_INFO @ 206283394.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_full_mem_access	87095418511799727165022120848142348405665661274977681731787433364327689761119	275581	UVM_INFO @ 101158002.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_full_mem_access	102008379353370656790243085763065857573967143639112725245353094029022081697713	275581	UVM_INFO @ 81986291.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				4 test runs
	flash_ctrl_rw	29477614888640613941434554923568139599562808785361630072410298350100153492089	None
	flash_ctrl_rw	35231472754393668704920196593701813293958409650134759966316426550089898558360	None
	flash_ctrl_rw	7071665054019401566652185495443581992508422148978430851879041633143585511964	None
	flash_ctrl_rw	97402567094348052108964099777267460617276045099862353990640240586245797819053	None
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue				2 test runs
	flash_ctrl_integrity	70450913105130885266703908377968126973928406778944868161559521299507155271626	114	UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_integrity	31503718095316934361750700724039621056977004468732958825671951270508145553484	114	UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value:				2 test runs
	flash_ctrl_rw_evict	37462324913575218230528521939718802362435569135327190016274171897639264740462	114	UVM_INFO @ 66142.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	105193499634112435685158051521544243433380632172361592335549542181419788865509	114	UVM_INFO @ 19608.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$fell(src_ack_o)'				1 test run
	flash_ctrl_hw_rma	7616403481808778817237490884068546626376879050383886701393523606016321061795	175	UVM_ERROR @ 101067121.9 ns: (prim_sync_reqack.sv:357) [ASSERT FAILED] SyncReqAckHoldReq UVM_INFO @ 101067121.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp _e521f5ce:ffffffff_e521f5ce mismatch!!				1 test run
	flash_ctrl_intr_rd	41324716575722878013468036796597118363722975913407617637743324583961821945134	114	UVM_INFO @ 6120499.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending 'dst_req_o'				1 test run
	flash_ctrl_otp_reset	58375057616641003392852242089172616418688010094302456915574455383844739587132	163	UVM_ERROR @ 131780.7 ns: (prim_sync_reqack.sv:364) [ASSERT FAILED] SyncReqAckAckNeedsReq UVM_INFO @ 131780.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp fcd9c5a4_94c91f11:ffffffff_94c91f mismatch!!				1 test run
	flash_ctrl_intr_rd	26213676313308378778145860141825019352026770488097946576981301275571699402541	114	UVM_INFO @ 658393.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:				1 test run
	flash_ctrl_rw_evict	33787985344502206851158916466987050604979202182653027112116258216043127372101	114	UVM_INFO @ 23897.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---