Simulation Results: hmac

 
15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.81 %
  • code
  • 99.20 %
  • assert
  • 97.60 %
  • func
  • 99.62 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.57 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 13.810s 3518.398us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.910s 45.577us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.200s 48.916us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.810s 1217.699us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.730s 1714.258us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 651.650s 309566.994us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.200s 48.916us 5 5 100.00
hmac_csr_aliasing 6.730s 1714.258us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 81.170s 36273.774us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 98.600s 2487.099us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 281.590s 42277.917us 30 30 100.00
hmac_test_sha384_vectors 522.820s 20835.333us 75 75 100.00
hmac_test_sha512_vectors 583.340s 22539.756us 75 75 100.00
hmac_test_hmac256_vectors 15.400s 868.586us 50 50 100.00
hmac_test_hmac384_vectors 15.590s 3634.503us 60 60 100.00
hmac_test_hmac512_vectors 19.010s 1111.084us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 39.730s 4145.799us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 970.870s 34611.323us 10 10 100.00
error 10 10 100.00
hmac_error 120.710s 3538.497us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 122.660s 3431.677us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 13.810s 3518.398us 10 10 100.00
hmac_long_msg 81.170s 36273.774us 10 10 100.00
hmac_back_pressure 98.600s 2487.099us 25 25 100.00
hmac_datapath_stress 970.870s 34611.323us 10 10 100.00
hmac_burst_wr 39.730s 4145.799us 50 50 100.00
hmac_stress_all 3402.920s 266483.760us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 13.810s 3518.398us 10 10 100.00
hmac_long_msg 81.170s 36273.774us 10 10 100.00
hmac_back_pressure 98.600s 2487.099us 25 25 100.00
hmac_datapath_stress 970.870s 34611.323us 10 10 100.00
hmac_wipe_secret 122.660s 3431.677us 10 10 100.00
hmac_test_sha256_vectors 281.590s 42277.917us 30 30 100.00
hmac_test_sha384_vectors 522.820s 20835.333us 75 75 100.00
hmac_test_sha512_vectors 583.340s 22539.756us 75 75 100.00
hmac_test_hmac256_vectors 15.400s 868.586us 50 50 100.00
hmac_test_hmac384_vectors 15.590s 3634.503us 60 60 100.00
hmac_test_hmac512_vectors 19.010s 1111.084us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 13.810s 3518.398us 10 10 100.00
hmac_long_msg 81.170s 36273.774us 10 10 100.00
hmac_back_pressure 98.600s 2487.099us 25 25 100.00
hmac_datapath_stress 970.870s 34611.323us 10 10 100.00
hmac_burst_wr 39.730s 4145.799us 50 50 100.00
hmac_error 120.710s 3538.497us 10 10 100.00
hmac_wipe_secret 122.660s 3431.677us 10 10 100.00
hmac_test_sha256_vectors 281.590s 42277.917us 30 30 100.00
hmac_test_sha384_vectors 522.820s 20835.333us 75 75 100.00
hmac_test_sha512_vectors 583.340s 22539.756us 75 75 100.00
hmac_test_hmac256_vectors 15.400s 868.586us 50 50 100.00
hmac_test_hmac384_vectors 15.590s 3634.503us 60 60 100.00
hmac_test_hmac512_vectors 19.010s 1111.084us 75 75 100.00
hmac_stress_all 3402.920s 266483.760us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 3402.920s 266483.760us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.920s 42.391us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.960s 18.744us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 4.430s 1021.501us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 4.430s 1021.501us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 0.910s 45.577us 1 1 100.00
hmac_csr_rw 1.200s 48.916us 5 5 100.00
hmac_csr_aliasing 6.730s 1714.258us 1 1 100.00
hmac_same_csr_outstanding 2.140s 136.554us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 0.910s 45.577us 1 1 100.00
hmac_csr_rw 1.200s 48.916us 5 5 100.00
hmac_csr_aliasing 6.730s 1714.258us 1 1 100.00
hmac_same_csr_outstanding 2.140s 136.554us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.630s 430.039us 5 5 100.00
hmac_tl_intg_err 4.900s 1142.869us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 4.900s 1142.869us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 13.810s 3518.398us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 8.600s 628.451us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 377.270s 6931.143us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.990s 13.184us 1 1 100.00