Simulation Results: keymgr

 
15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.77 %
  • code
  • 98.36 %
  • assert
  • 97.72 %
  • func
  • 91.22 %
  • line
  • 99.20 %
  • branch
  • 99.18 %
  • cond
  • 97.96 %
  • toggle
  • 97.79 %
  • FSM
  • 97.67 %
Validation stages
V1
100.00%
V2
99.30%
V2S
99.69%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 30 30 100.00
keymgr_smoke 3.080s 132.095us 30 30 100.00
random 30 30 100.00
keymgr_random 5.310s 973.407us 30 30 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.310s 18.048us 1 1 100.00
csr_rw 5 5 100.00
keymgr_csr_rw 1.390s 53.694us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 21.560s 3174.386us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 3.870s 279.317us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_csr_mem_rw_with_rand_reset 1.960s 33.869us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_csr_rw 1.390s 53.694us 5 5 100.00
keymgr_csr_aliasing 3.870s 279.317us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 3.890s 92.258us 50 50 100.00
sideload 80 80 100.00
keymgr_sideload 3.050s 88.935us 20 20 100.00
keymgr_sideload_kmac 3.470s 512.892us 20 20 100.00
keymgr_sideload_aes 3.810s 611.592us 20 20 100.00
keymgr_sideload_otbn 3.320s 198.644us 20 20 100.00
direct_to_disabled_state 30 30 100.00
keymgr_direct_to_disabled 3.450s 590.300us 30 30 100.00
lc_disable 50 50 100.00
keymgr_lc_disable 4.080s 114.700us 50 50 100.00
kmac_error_response 20 20 100.00
keymgr_kmac_rsp_err 5.810s 412.279us 20 20 100.00
invalid_sw_input 20 20 100.00
keymgr_sw_invalid_input 5.640s 887.829us 20 20 100.00
invalid_hw_input 49 50 98.00
keymgr_hwsw_invalid_input 5.690s 696.438us 49 50 98.00
sync_async_fault_cross 20 20 100.00
keymgr_sync_async_fault_cross 2.900s 251.873us 20 20 100.00
stress_all 48 50 96.00
keymgr_stress_all 38.700s 9174.638us 48 50 96.00
intr_test 10 10 100.00
keymgr_intr_test 1.090s 65.724us 10 10 100.00
alert_test 10 10 100.00
keymgr_alert_test 1.110s 15.531us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_tl_errors 4.350s 281.349us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_tl_errors 4.350s 281.349us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_csr_hw_reset 1.310s 18.048us 1 1 100.00
keymgr_csr_rw 1.390s 53.694us 5 5 100.00
keymgr_csr_aliasing 3.870s 279.317us 1 1 100.00
keymgr_same_csr_outstanding 3.830s 542.250us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_csr_hw_reset 1.310s 18.048us 1 1 100.00
keymgr_csr_rw 1.390s 53.694us 5 5 100.00
keymgr_csr_aliasing 3.870s 279.317us 1 1 100.00
keymgr_same_csr_outstanding 3.830s 542.250us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 12.670s 7934.376us 5 5 100.00
tl_intg_err 30 30 100.00
keymgr_sec_cm 12.670s 7934.376us 5 5 100.00
keymgr_tl_intg_err 8.610s 557.749us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 4.460s 277.570us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 4.460s 277.570us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 4.460s 277.570us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 4.460s 277.570us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 11.870s 2270.019us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 12.670s 7934.376us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 12.670s 7934.376us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
keymgr_tl_intg_err 8.610s 557.749us 25 25 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 4.460s 277.570us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 3.890s 92.258us 50 50 100.00
sec_cm_reseed_config_regwen 35 35 100.00
keymgr_random 5.310s 973.407us 30 30 100.00
keymgr_csr_rw 1.390s 53.694us 5 5 100.00
sec_cm_sw_binding_config_regwen 35 35 100.00
keymgr_random 5.310s 973.407us 30 30 100.00
keymgr_csr_rw 1.390s 53.694us 5 5 100.00
sec_cm_max_key_ver_config_regwen 35 35 100.00
keymgr_random 5.310s 973.407us 30 30 100.00
keymgr_csr_rw 1.390s 53.694us 5 5 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
keymgr_lc_disable 4.080s 114.700us 50 50 100.00
sec_cm_constants_consistency 49 50 98.00
keymgr_hwsw_invalid_input 5.690s 696.438us 49 50 98.00
sec_cm_intersig_consistency 49 50 98.00
keymgr_hwsw_invalid_input 5.690s 696.438us 49 50 98.00
sec_cm_hw_key_sw_noaccess 30 30 100.00
keymgr_random 5.310s 973.407us 30 30 100.00
sec_cm_output_keys_ctrl_redun 20 20 100.00
keymgr_sideload_protect 4.340s 608.973us 20 20 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.670s 7934.376us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.670s 7934.376us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 12.670s 7934.376us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 4.170s 213.673us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 50 50 100.00
keymgr_lc_disable 4.080s 114.700us 50 50 100.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 12.670s 7934.376us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.670s 7934.376us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 12.670s 7934.376us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 4.170s 213.673us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 4.170s 213.673us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 12.670s 7934.376us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 4.170s 213.673us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 12.670s 7934.376us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 4.170s 213.673us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 16 20 80.00
keymgr_stress_all_with_rand_reset 15.610s 7626.681us 16 20 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
keymgr_stress_all_with_rand_reset 32769434245241986342661914605901007242601332819598495006517707131848805444019 1749
UVM_INFO @ 7626680852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 11025698349998069046243285518880693082916681472558341506301910413544037387269 2234
UVM_INFO @ 2996999906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 55771202962493694217463349306175186298138222364059444831634332385974475697530 2008
UVM_INFO @ 1010241760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 52384963793117388335781787224722443047124247012393063176238945703231753416986 1277
UVM_INFO @ 641758676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:778) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_* 1 test run
keymgr_stress_all 115243678335908357904186094605293207015342631063681088724785236402908333757980 1200
UVM_INFO @ 911746323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:663) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*]) 1 test run
keymgr_stress_all 45664824108930658879296916756680289563043720342791198624268707803969437908729 1440
UVM_INFO @ 474738648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* 1 test run
keymgr_hwsw_invalid_input 81156060180316901049726321134714624343900013604379386629412160700923556522148 208
UVM_INFO @ 10276096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---