Simulation Results: lc_ctrl/volatile_unlock_disabled

 
15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.20 %
  • code
  • 85.88 %
  • assert
  • 94.83 %
  • func
  • 95.88 %
  • line
  • 97.28 %
  • branch
  • 94.00 %
  • cond
  • 81.55 %
  • toggle
  • 88.33 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 6.900s 226.630us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.280s 18.216us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.280s 31.755us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.850s 56.267us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.780s 720.796us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.620s 187.225us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.280s 31.755us 5 5 100.00
lc_ctrl_csr_aliasing 1.780s 720.796us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 9.560s 129.640us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 9.790s 887.946us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.180s 15.688us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.510s 423.127us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 14.240s 1247.945us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 9.280s 444.618us 19 20 95.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 14.240s 1247.945us 20 20 100.00
lc_ctrl_prog_failure 3.510s 423.127us 20 20 100.00
lc_ctrl_errors 9.280s 444.618us 19 20 95.00
lc_ctrl_security_escalation 10.320s 974.434us 20 20 100.00
lc_ctrl_jtag_state_failure 60.620s 4109.311us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.310s 655.186us 20 20 100.00
lc_ctrl_jtag_errors 38.740s 10122.467us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 10.880s 2772.023us 20 20 100.00
lc_ctrl_jtag_state_post_trans 17.500s 5368.396us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.310s 655.186us 20 20 100.00
lc_ctrl_jtag_errors 38.740s 10122.467us 20 20 100.00
lc_ctrl_jtag_access 12.660s 2117.956us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 22.830s 2597.357us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 2.520s 121.409us 10 10 100.00
lc_ctrl_jtag_csr_rw 1.840s 126.833us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 11.130s 2014.392us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 6.720s 3856.289us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.570s 23.320us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.970s 155.359us 10 10 100.00
lc_ctrl_jtag_alert_test 1.770s 161.217us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 9.790s 5858.616us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.290s 14.017us 10 10 100.00
stress_all 9 10 90.00
lc_ctrl_stress_all 158.190s 27037.836us 9 10 90.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.420s 94.016us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 3.540s 128.997us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 3.540s 128.997us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.280s 18.216us 1 1 100.00
lc_ctrl_csr_rw 1.280s 31.755us 5 5 100.00
lc_ctrl_csr_aliasing 1.780s 720.796us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.850s 55.327us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.280s 18.216us 1 1 100.00
lc_ctrl_csr_rw 1.280s 31.755us 5 5 100.00
lc_ctrl_csr_aliasing 1.780s 720.796us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.850s 55.327us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 10.480s 2308.747us 5 5 100.00
lc_ctrl_tl_intg_err 3.000s 258.390us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.000s 258.390us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 9.790s 887.946us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 14.240s 1247.945us 20 20 100.00
lc_ctrl_sec_cm 10.480s 2308.747us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 14.240s 1247.945us 20 20 100.00
lc_ctrl_sec_cm 10.480s 2308.747us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 14.240s 1247.945us 20 20 100.00
lc_ctrl_sec_cm 10.480s 2308.747us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 14.240s 1247.945us 20 20 100.00
lc_ctrl_sec_cm 10.480s 2308.747us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 14.240s 1247.945us 20 20 100.00
lc_ctrl_sec_cm 10.480s 2308.747us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 14.240s 1247.945us 20 20 100.00
lc_ctrl_sec_cm 10.480s 2308.747us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 14.240s 1247.945us 20 20 100.00
lc_ctrl_sec_cm 10.480s 2308.747us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 14.240s 1247.945us 20 20 100.00
lc_ctrl_sec_cm 10.480s 2308.747us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 10.320s 974.434us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 9.560s 129.640us 20 20 100.00
lc_ctrl_jtag_state_post_trans 17.500s 5368.396us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 8.170s 374.298us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 8.170s 374.298us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 14.290s 1880.511us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 7.290s 1305.616us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 7.290s 1305.616us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
lc_ctrl_stress_all_with_rand_reset 54.030s 51225.650us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
lc_ctrl_stress_all_with_rand_reset 12888746979228174145480413438675065606227265072853924688196960931192672913829 6865
UVM_INFO @ 3688071910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 61920064905843003696823846663577820708705116789194361640302674603900110039770 8822
UVM_INFO @ 18691645144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_stress_all 68671849183314166835118315615672269836386333674042606886143255736940218741694 10857
UVM_INFO @ 23806259161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 105120730677246655779856365074531218034757647853382889225907478985447646526778 1947
UVM_INFO @ 762976772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---