Simulation Results: lc_ctrl/volatile_unlock_enabled

 
15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.47 %
  • code
  • 86.02 %
  • assert
  • 94.97 %
  • func
  • 96.42 %
  • line
  • 97.26 %
  • branch
  • 93.80 %
  • cond
  • 81.55 %
  • toggle
  • 88.33 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.06%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 3.490s 1017.350us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.270s 23.636us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.250s 70.192us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.660s 59.744us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.380s 223.783us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.530s 19.352us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.250s 70.192us 5 5 100.00
lc_ctrl_csr_aliasing 1.380s 223.783us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 9.590s 69.984us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 11.540s 786.413us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.120s 14.615us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.220s 112.975us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 11.260s 2149.605us 20 20 100.00
lc_errors 18 20 90.00
lc_ctrl_errors 9.040s 1385.883us 18 20 90.00
security_escalation 136 140 97.14
lc_ctrl_state_failure 11.260s 2149.605us 20 20 100.00
lc_ctrl_prog_failure 3.220s 112.975us 20 20 100.00
lc_ctrl_errors 9.040s 1385.883us 18 20 90.00
lc_ctrl_security_escalation 8.300s 324.835us 20 20 100.00
lc_ctrl_jtag_state_failure 39.970s 3149.039us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.070s 766.223us 20 20 100.00
lc_ctrl_jtag_errors 32.550s 2826.686us 18 20 90.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 5.820s 401.697us 20 20 100.00
lc_ctrl_jtag_state_post_trans 15.800s 4073.243us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.070s 766.223us 20 20 100.00
lc_ctrl_jtag_errors 32.550s 2826.686us 18 20 90.00
lc_ctrl_jtag_access 8.750s 1224.780us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 16.870s 2209.255us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 2.150s 877.837us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.080s 196.491us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 12.230s 4090.713us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 7.340s 2376.665us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.590s 23.668us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.110s 180.520us 10 10 100.00
lc_ctrl_jtag_alert_test 1.670s 399.545us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 16.080s 2256.818us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.280s 15.764us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 135.650s 41108.254us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.490s 174.654us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 3.700s 267.104us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 3.700s 267.104us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.270s 23.636us 1 1 100.00
lc_ctrl_csr_rw 1.250s 70.192us 5 5 100.00
lc_ctrl_csr_aliasing 1.380s 223.783us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.290s 93.135us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.270s 23.636us 1 1 100.00
lc_ctrl_csr_rw 1.250s 70.192us 5 5 100.00
lc_ctrl_csr_aliasing 1.380s 223.783us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.290s 93.135us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 7.680s 240.545us 5 5 100.00
lc_ctrl_tl_intg_err 3.120s 136.324us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.120s 136.324us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 11.540s 786.413us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 11.260s 2149.605us 20 20 100.00
lc_ctrl_sec_cm 7.680s 240.545us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 11.260s 2149.605us 20 20 100.00
lc_ctrl_sec_cm 7.680s 240.545us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 11.260s 2149.605us 20 20 100.00
lc_ctrl_sec_cm 7.680s 240.545us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 11.260s 2149.605us 20 20 100.00
lc_ctrl_sec_cm 7.680s 240.545us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 11.260s 2149.605us 20 20 100.00
lc_ctrl_sec_cm 7.680s 240.545us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 11.260s 2149.605us 20 20 100.00
lc_ctrl_sec_cm 7.680s 240.545us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 11.260s 2149.605us 20 20 100.00
lc_ctrl_sec_cm 7.680s 240.545us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 11.260s 2149.605us 20 20 100.00
lc_ctrl_sec_cm 7.680s 240.545us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 8.300s 324.835us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 9.590s 69.984us 20 20 100.00
lc_ctrl_jtag_state_post_trans 15.800s 4073.243us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 7.630s 548.780us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 7.630s 548.780us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 10.630s 858.148us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 5.800s 692.147us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 5.800s 692.147us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 44.240s 12970.958us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
lc_ctrl_stress_all_with_rand_reset 97322660828584453590358052767740474720474353698669349670182231178266655593898 5351
UVM_INFO @ 4783397583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 18501741923866516159343264352780148983259413979071945005574232590910751314458 8160
UVM_INFO @ 12970957656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 75436696969415253716414974630686929549441759998384730415157330215608533139899 7005
UVM_INFO @ 9956663145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 65814966350505877892965226756429417968147828890940483371656530066547232303097 541
UVM_INFO @ 6042094393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 87322045512636938908074563905038059854101448216893681292728759839730702901268 7674
UVM_INFO @ 4646711831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 25742294264631464659983121929869756347781620896858647753441176455518803875965 173
UVM_INFO @ 235750199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 4 test runs
lc_ctrl_jtag_errors 55819060336071802010857909429392763382088078871661327471413091485331800069681 460
UVM_INFO @ 142395026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 583271627780596312602841388402178540568822944963882930339837176711920178070 1331
UVM_INFO @ 757207430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 19772040398823198893143954728303872600855626863351636907856544209050863383597 2158
UVM_INFO @ 160873389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 83536151488085244561401882055414095501061962181393957845955505788806175896007 670
UVM_INFO @ 134316616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---