Simulation Results: otp_ctrl

 
15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.09 %
  • code
  • 85.45 %
  • assert
  • 95.53 %
  • func
  • 92.30 %
  • line
  • 90.33 %
  • branch
  • 86.85 %
  • cond
  • 93.94 %
  • toggle
  • 92.58 %
  • FSM
  • 63.54 %
Validation stages
V1
96.15%
V2
96.95%
V2S
97.12%
V3
15.84%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.790s 55.767us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 12.320s 1327.260us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.100s 1079.623us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 1.820s 127.623us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.360s 158.431us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.200s 178.734us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
otp_ctrl_csr_mem_rw_with_rand_reset 4.140s 1138.894us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 1.820s 127.623us 5 5 100.00
otp_ctrl_csr_aliasing 5.200s 178.734us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.350s 49.057us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.090s 564.266us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.270s 365.663us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 6.870s 3054.342us 300 300 100.00
partition_check 45 60 75.00
otp_ctrl_background_chks 35.520s 7249.004us 10 10 100.00
otp_ctrl_check_fail 41.180s 8452.952us 35 50 70.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 13.130s 5141.457us 30 30 100.00
partition_lock 30 30 100.00
otp_ctrl_dai_lock 56.180s 6184.869us 30 30 100.00
interface_key_check 10 10 100.00
otp_ctrl_parallel_key_req 29.300s 5949.631us 10 10 100.00
lc_interactions 209 210 99.52
otp_ctrl_parallel_lc_req 17.380s 753.186us 10 10 100.00
otp_ctrl_parallel_lc_esc 51.730s 10010.294us 199 200 99.50
otp_dai_errors 22 25 88.00
otp_ctrl_dai_errs 56.450s 27667.848us 22 25 88.00
otp_macro_errors 7 10 70.00
otp_ctrl_macro_errs 19.060s 2899.593us 7 10 70.00
test_access 10 10 100.00
otp_ctrl_test_access 91.330s 11345.795us 10 10 100.00
stress_all 9 10 90.00
otp_ctrl_stress_all 381.600s 32115.534us 9 10 90.00
intr_test 10 10 100.00
otp_ctrl_intr_test 1.830s 87.502us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 2.540s 204.635us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 9.390s 3219.634us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 9.390s 3219.634us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.100s 1079.623us 1 1 100.00
otp_ctrl_csr_rw 1.820s 127.623us 5 5 100.00
otp_ctrl_csr_aliasing 5.200s 178.734us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.640s 281.731us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.100s 1079.623us 1 1 100.00
otp_ctrl_csr_rw 1.820s 127.623us 5 5 100.00
otp_ctrl_csr_aliasing 5.200s 178.734us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.640s 281.731us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
tl_intg_err 30 30 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
otp_ctrl_tl_intg_err 38.640s 20331.418us 25 25 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
otp_ctrl_tl_intg_err 38.640s 20331.418us 25 25 100.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 12.320s 1327.260us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 12.320s 1327.260us 10 10 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_dai_fsm_local_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 51.730s 10010.294us 199 200 99.50
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_lci_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 51.730s 10010.294us 199 200 99.50
sec_cm_kdi_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 51.730s 10010.294us 199 200 99.50
sec_cm_part_fsm_local_esc 206 210 98.10
otp_ctrl_parallel_lc_esc 51.730s 10010.294us 199 200 99.50
otp_ctrl_macro_errs 19.060s 2899.593us 7 10 70.00
sec_cm_scrmbl_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 51.730s 10010.294us 199 200 99.50
sec_cm_timer_fsm_local_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 51.730s 10010.294us 199 200 99.50
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_dai_fsm_global_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 51.730s 10010.294us 199 200 99.50
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_lci_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 51.730s 10010.294us 199 200 99.50
sec_cm_kdi_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 51.730s 10010.294us 199 200 99.50
sec_cm_part_fsm_global_esc 206 210 98.10
otp_ctrl_parallel_lc_esc 51.730s 10010.294us 199 200 99.50
otp_ctrl_macro_errs 19.060s 2899.593us 7 10 70.00
sec_cm_scrmbl_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 51.730s 10010.294us 199 200 99.50
sec_cm_timer_fsm_global_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 51.730s 10010.294us 199 200 99.50
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 6.870s 3054.342us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 35 50 70.00
otp_ctrl_check_fail 41.180s 8452.952us 35 50 70.00
sec_cm_part_mem_regren 30 30 100.00
otp_ctrl_dai_lock 56.180s 6184.869us 30 30 100.00
sec_cm_part_mem_sw_unreadable 30 30 100.00
otp_ctrl_dai_lock 56.180s 6184.869us 30 30 100.00
sec_cm_part_mem_sw_unwritable 30 30 100.00
otp_ctrl_dai_lock 56.180s 6184.869us 30 30 100.00
sec_cm_lc_part_mem_sw_noaccess 30 30 100.00
otp_ctrl_dai_lock 56.180s 6184.869us 30 30 100.00
sec_cm_access_ctrl_mubi 30 30 100.00
otp_ctrl_dai_lock 56.180s 6184.869us 30 30 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 12.320s 1327.260us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 30 30 100.00
otp_ctrl_dai_lock 56.180s 6184.869us 30 30 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 12.320s 1327.260us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 273.360s 175182.749us 5 5 100.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 13.130s 5141.457us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 12.320s 1327.260us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 12.320s 1327.260us 10 10 100.00
sec_cm_macro_mem_integrity 7 10 70.00
otp_ctrl_macro_errs 19.060s 2899.593us 7 10 70.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 13.740s 7915.051us 1 1 100.00
stress_all_with_rand_reset 15 100 15.00
otp_ctrl_stress_all_with_rand_reset 3600.130s 0.000us 15 100 15.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 31 test runs
otp_ctrl_check_fail 35238415282938829090694814807164763967813214118970835515303166146872071748736 3338
UVM_INFO @ 250719402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 108732463585927078775419174690229479219651024738230667480833058677622098331973 661
UVM_INFO @ 245515373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 61983738117174797285311176009709556238888629163104187148352349416365840650295 2384
UVM_INFO @ 1889659495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 3431727129596650480413480725291533368547226202592785701856284520097510698707 151487
UVM_INFO @ 29891778598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 30273988604233718941722211437181702370071626781457025401576581403295549559802 11457
UVM_INFO @ 18172457226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 102283716721981068118959845261666908871356009394089232350105070841314131964114 4714
UVM_INFO @ 1952590122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 90841480794003940628442440991606825696019218425054756121640040270068030685263 4398
UVM_INFO @ 650985854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 99637422150493210164898227705027671157849933033205565771174695931406495708854 3303
UVM_INFO @ 739581614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 105344470599526892098451578095477503188926624112590614550636630407412874969867 12870
UVM_INFO @ 1558939549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 18617402854329225259035061472328173693519571832215126677993908777213512222392 2071
UVM_INFO @ 612342783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 99297659503989045849192510609867698215814776478437380826989869361689771721909 2109
UVM_INFO @ 1020212037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 32329959487841333726467279039219757271670796057152676998024436177749534917470 2169
UVM_INFO @ 187171311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23889797674358286172133048178288733008788730435754129012108488018786632691520 195
UVM_INFO @ 52528134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 43216805097937912817003843773230778571270410153387323307808413468369982491797 6229
UVM_INFO @ 1064281815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 42361565587699151298202450198506051205715093017462555521647219861756487181551 3410
UVM_INFO @ 2572303692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 26031233369274618640469879743796592549751840214215751440929538370410150004970 2085
UVM_INFO @ 236226620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 112830910414441924150921605747482490067982416510722210069969455082403897752922 16940
UVM_INFO @ 25777734854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 21582985468816982809228249751275724135353851824334810275250867081428483755993 1806
UVM_INFO @ 215595171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 91458992013557081304249716015412086510056919380457906504009707460164782964642 1803
UVM_INFO @ 305115084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 102456592285270134682777705862718254972204446597417084636676603404924295308910 2638
UVM_INFO @ 1214325004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28199363693452600995891723657507823418524544470064370605035436905398865979512 12112
UVM_INFO @ 2560847634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 70913618354463501124435256852944018701936103128272901253782514094941510863809 3636
UVM_INFO @ 2322881390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 30327605813665137873308788396456788367856666641606099493364099935729858767741 5805
UVM_INFO @ 2740314086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112679916337065376797672214012879820290616067005936070642587773733221528329857 3787
UVM_INFO @ 250982301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23577892877289676495353498998890643546046268909192238405491578069589994713371 1486
UVM_INFO @ 533456768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45389869851697204817724189488458698555678623814435592075202354090303290645402 9286
UVM_INFO @ 25032433980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4672517138062227008170105303729858977689378313183539755358786074845566149025 18057
UVM_INFO @ 2264161780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2413978162753898363430987408634509143590283946045763248634855928179292563796 2122
UVM_INFO @ 5902932889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44009718206023742526113078848523777026760491435436325715203340730956844231084 511
UVM_INFO @ 87039539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62481104002995608743646169908127956001597085219770486463159260903910760004194 157
UVM_INFO @ 566619442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 21748988493249548800768888166440926425853663328747884084183535963732708812030 18497
UVM_INFO @ 4605200269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 28 test runs
otp_ctrl_stress_all_with_rand_reset 100264567118876695553926670260259404758629407957377785488300487305129619783856 908
UVM_INFO @ 329167405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4670051499465248169389303679544269539600165268170972762934289216583155376983 4150
UVM_INFO @ 4431009425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91489288964501786831736618446970197317031153042076983296760547712301860464424 5533
UVM_INFO @ 6222750422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61282074180737393907246375909589375663933533481525505065190984268540623114461 119
UVM_INFO @ 136639173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 9582530051000469603512275743759893093574863578847912313300610601019715778002 8421
UVM_INFO @ 1025278981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12971886237029392297457423704850260803437726972566857862524050594365586087200 17409
UVM_INFO @ 1699283767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 97557374296095073022233953428895626935846141397211537295213252349497636148428 1177
UVM_INFO @ 164161408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54080153222890685744323982833775135293463425928015957968133427000452065110601 117
UVM_INFO @ 43518417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 39159824486993323585243166866789317919240104550741299244157343182970499091683 185
UVM_INFO @ 55678946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38536255961927329611745078218736329632974896077757982071966696964041024172929 5787
UVM_INFO @ 1872298271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 501941304781566254990740999814234162089612266329491422445402902191758022096 2430
UVM_INFO @ 773928760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 39886895119970660388138506428832782054234299124077750521719101616343626686833 19924
UVM_INFO @ 4625366687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48608356426857982919593583259916809821441913579855823058396322264445349651349 3950
UVM_INFO @ 11128331698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82816539982108715675825903750918296578253319691212071217711911822636878440274 15264
UVM_INFO @ 2901240933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62392291590947756750181594068466762712096764941620829096708553461148238500253 3632
UVM_INFO @ 643788345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 67679934552965817333774547350750428558090864884380724494155272240762905769825 4259
UVM_INFO @ 695587920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 9051284065332315958679627613029051231261599050157754383312395472810583522305 11341
UVM_INFO @ 3034870156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73555992015866123124818670049646115477168075831496625155386438379275624413229 157
UVM_INFO @ 148128657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 101480284630639045658923713057792824102822075288950439422966084800721016346647 175
UVM_INFO @ 140078568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29102350425598537598328849143567057861228185175165897984403047041652360721142 5633
UVM_INFO @ 1350074477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 24119194307963676843458694967253048031160686422437763426110855996716137152706 7523
UVM_INFO @ 27242042166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 9643834380593983010863487163789948686269531896088732370709594282860717453374 1166
UVM_INFO @ 784795238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28975386811793216455879230441909442350664177951551958120658406319607871391105 8788
UVM_INFO @ 5519855983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23549851912815964045152961283739691768931462194898828852031552992530102259588 2477
UVM_INFO @ 2435002475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50153498487465460963635694059452754316111592888414856847463301042174255999057 14186
UVM_INFO @ 7987327787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114965152960908193672156464063837707471788002157687632622850063018130847465391 159
UVM_INFO @ 39233192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 74390904492390098174728456384137971184358599718886770551867883232637633507792 8669
UVM_INFO @ 13394272458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38747243660009799778702506420082626374519935123244531407593254250368709432864 5638
UVM_INFO @ 11779853277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1824) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 25 test runs
otp_ctrl_stress_all_with_rand_reset 83624422100202817766193745003631914809319377340743892388179480803419262918100 3117
UVM_INFO @ 738372961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82596816901753122423584257728337757719557024298132962152830391261582553265222 9407
UVM_INFO @ 1022974679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 83104160339132082785970478124450747318889109480529571043130507842802822912087 13351
UVM_INFO @ 5802009424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2266701107466605785563702851159254289877640807031814094041176542750252574972 16534
UVM_INFO @ 4370286028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45330661997882696817823168011782245994426071225576953107304808225177192797991 61330
UVM_INFO @ 18459306901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 729714064444665932730408036353858535653213828666713576058775791042395983961 24275
UVM_INFO @ 6283745620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50844045222476174640550672780705760779570310609293174130735722382969179550587 60818
UVM_INFO @ 37065917796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18689780516681885823640441538571364182550482620501684246704185173626971082964 98
UVM_INFO @ 54133715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45714545452167316785471061317284667758683670793640917799363987199385596096978 27210
UVM_INFO @ 14707055053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29165411754871106725813408810923713948648151125864452813200188824455875956886 3560
UVM_INFO @ 4102392571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 49176798382201692533467473146673690856182461210069210938317320005842302112178 99
UVM_INFO @ 427984274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 32918035447247915152531898729221890773962095876619945521358463076443376727100 23876
UVM_INFO @ 3635337149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 101757678110238893365248239135107646877933889455515545037825939790373592027 22901
UVM_INFO @ 1291721177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 56393436214375255764984400279736762573881370718676867009662917398330473736625 98
UVM_INFO @ 57869181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61913280186936248131917620900945143814511147732041350186271311594542842778567 98
UVM_INFO @ 107524819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45015275085363022589519416677668179351202599216246587588005544200716735223898 3112
UVM_INFO @ 663028492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 113950176044747944842134361892580467001694123510190279505156632271615783435182 98
UVM_INFO @ 425975591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 92898321901805306333631330888091057951466616939770539850615553648554144292268 18338
UVM_INFO @ 59191837327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 27186467054345262466393453687169950260756636017413974628110032035165187679128 26217
UVM_INFO @ 11539610658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 83470425623734876439304010648553579076160741108593851624309341814206061366222 21733
UVM_INFO @ 1953669551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50640092910023772385851976301055962885865402098193132184151286536899981831159 98
UVM_INFO @ 431829888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 6387071388536911211420081298963032557135799470430883023618087634381468360765 7565
UVM_INFO @ 24102414914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 75829765033013400384589597200577921044872975168775332185112013706270477183305 292
UVM_INFO @ 220519411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 34495494314349109496713099653167148028186723901484256935221404629218887644199 364
UVM_INFO @ 670562315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 56825304828003670661618022158413600243357965140103622412566755956458049868008 86422
UVM_INFO @ 13012049803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:692) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 14 test runs
otp_ctrl_stress_all_with_rand_reset 102790456305808205905542789986370873468764642872798122390076682747917552955744 98
UVM_INFO @ 70574390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 101549166986987064401846607677260576720098465766087820253894316287142208356282 184
UVM_INFO @ 111973108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51543155477487893117743352187046484984016548019498272032648706871579127808419 23270
UVM_INFO @ 28846545795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 41728296662052529355190634695903256714379842356875880729436151777046228286584 2703
UVM_INFO @ 649179703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59770665348447915013948560887915803356017169611541996331307682656788199982365 98
UVM_INFO @ 27094587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45184800382999868343051314889766229259158339769955221526246990168843913361141 1184
UVM_INFO @ 605527784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 97175346468028686017067653385601113468811111662502681905650054415862494816043 99
UVM_INFO @ 112393329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 96555323563363683161937710292828137470618760693446016832335866308173108131350 99
UVM_INFO @ 27778124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42312694134697657130372443081008249596850804179790241945244503592625967832166 98
UVM_INFO @ 107315298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 40202321615109543467225671177408006855211554715268001654940145405155776611734 7818
UVM_INFO @ 10276235151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 83684743405753179053429278488012245507422989004203062357962176842078939389578 10628
UVM_INFO @ 2123601835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5081977721938809753847783752342972762810847133914113868327762889638852449031 10630
UVM_INFO @ 1181398425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 36185689459205271126945380113428401274469452941450218754842325370992027856965 7863
UVM_INFO @ 1216092505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13604082004766407709269457823894858428876631307339904658598993883935235162340 18178
UVM_INFO @ 1265825743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' 2 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 74531173463840257473668765041322190025913726035538809945448872605001092454173 105
UVM_ERROR @ 247284857 ps: (otp_ctrl_if.sv:299) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 247284857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43455079227318798225591319713526238348540486666673958535320345789065430369451 3217
UVM_ERROR @ 10251143945 ps: (otp_ctrl_if.sv:299) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 10251143945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen 2 test runs
otp_ctrl_stress_all_with_rand_reset 41446855591361989320362894787833756150016832174809297490280175590489985164833 7004
UVM_INFO @ 24520240733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 24932237616963207707929441184417977185352947110369054295746628247553816243475 13978
UVM_INFO @ 4844255274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:694) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_dai_errs 77267556376836315634951056423132472593620489412959587174307261050913787101775 1971
UVM_INFO @ 1089963670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_stress_all_with_rand_reset 31677827616171882399037773945674861157866806791635851348110389915609221027587 8015
UVM_INFO @ 29219851920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed 1 test run
otp_ctrl_stress_all_with_rand_reset 106695882027627810055100947652858490980966188557995291342179356206167513524598 9087
UVM_INFO @ 1761941839 ps: (otp_ctrl_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 1762025175 ps: (otp_ctrl_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 1762233515 ps: (otp_ctrl_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 1762243932 ps: (otp_ctrl_scoreboard.sv:592) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
Job timed out after * minutes 1 test run
otp_ctrl_stress_all_with_rand_reset 49101382804427802505397643687944357829006337189053445943409040382541100092647 None
UVM_ERROR (otp_ctrl_scoreboard.sv:283) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) 1 test run
otp_ctrl_stress_all_with_rand_reset 72927266049905146979824177991602115311700226364623955728402009262068924940728 9459
UVM_INFO @ 3150549541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 73798740583147189547695005540282706892540335350621350632992242818348595338587 22607
UVM_INFO @ 26222285365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_parallel_lc_esc_vseq] wait timeout occurred! 1 test run
otp_ctrl_parallel_lc_esc 105847967342778476735867051830222747302035981094136214757963390590137672897412 95
UVM_INFO @ 10010294075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---