Simulation Results: pwrmgr

 
15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.50 %
  • code
  • 97.54 %
  • assert
  • 98.96 %
  • func
  • 99.01 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.61 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
92.70%
V2S
99.13%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 0.770s 26.407us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.760s 25.098us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 0.820s 31.670us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.610s 189.146us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.880s 33.801us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.260s 99.401us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 0.820s 31.670us 5 5 100.00
pwrmgr_csr_aliasing 0.880s 33.801us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 0.980s 328.633us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 0.980s 328.633us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 0.910s 105.966us 10 10 100.00
pwrmgr_lowpower_invalid 0.910s 54.286us 10 10 100.00
reset 17 20 85.00
pwrmgr_reset 1.520s 1000.000us 9 10 90.00
pwrmgr_reset_invalid 1.020s 172.139us 8 10 80.00
main_power_glitch_reset 9 10 90.00
pwrmgr_reset 1.520s 1000.000us 9 10 90.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.200s 448.144us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.150s 300.745us 10 10 100.00
disable_rom_integrity_check 7 10 70.00
pwrmgr_disable_rom_integrity_check 2.400s 1000.000us 7 10 70.00
stress_all 6 10 60.00
pwrmgr_stress_all 20.940s 11420.225us 6 10 60.00
intr_test 10 10 100.00
pwrmgr_intr_test 0.880s 20.512us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwrmgr_tl_errors 2.140s 1155.957us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwrmgr_tl_errors 2.140s 1155.957us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 0.760s 25.098us 1 1 100.00
pwrmgr_csr_rw 0.820s 31.670us 5 5 100.00
pwrmgr_csr_aliasing 0.880s 33.801us 1 1 100.00
pwrmgr_same_csr_outstanding 0.960s 53.707us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 0.760s 25.098us 1 1 100.00
pwrmgr_csr_rw 0.820s 31.670us 5 5 100.00
pwrmgr_csr_aliasing 0.880s 33.801us 1 1 100.00
pwrmgr_same_csr_outstanding 0.960s 53.707us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
pwrmgr_tl_intg_err 1.770s 195.972us 25 25 100.00
pwrmgr_sec_cm 1.840s 689.196us 5 5 100.00
prim_count_check 5 5 100.00
pwrmgr_sec_cm 1.840s 689.196us 5 5 100.00
prim_fsm_check 5 5 100.00
pwrmgr_sec_cm 1.840s 689.196us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
pwrmgr_tl_intg_err 1.770s 195.972us 25 25 100.00
sec_cm_lc_ctrl_intersig_mubi 9 10 90.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.470s 779.614us 9 10 90.00
sec_cm_rom_ctrl_intersig_mubi 20 20 100.00
pwrmgr_wakeup_reset 1.200s 448.144us 10 10 100.00
pwrmgr_repeat_wakeup_reset 2.500s 694.612us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.000s 97.388us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 0.770s 30.096us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 5 5 100.00
pwrmgr_sec_cm 1.840s 689.196us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
pwrmgr_sec_cm 1.840s 689.196us 5 5 100.00
sec_cm_fsm_terminal 5 5 100.00
pwrmgr_sec_cm 1.840s 689.196us 5 5 100.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 0.760s 42.210us 10 10 100.00
sec_cm_main_pd_rst_local_esc 10 10 100.00
pwrmgr_glitch 0.870s 39.555us 10 10 100.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.990s 238.402us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.820s 31.670us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.820s 31.670us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 5 10 50.00
pwrmgr_escalation_timeout 0.900s 191.977us 5 10 50.00
stress_all_with_rand_reset 9 10 90.00
pwrmgr_stress_all_with_rand_reset 11.100s 24502.083us 9 10 90.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 5 test runs
pwrmgr_escalation_timeout 48414892677005695259265817600098028007877357116186002835362912983238778256770 85
UVM_ERROR @ 186828926 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 186828926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 79360475805160570700124093681917674875092770191153461333257501264394389577705 85
UVM_ERROR @ 188101855 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 188101855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 77932188174722574729962142487215497350248582227426896335268212952339949348807 85
UVM_ERROR @ 370658254 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 370658254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 5711315441242323165137735665495189985454629234554998143869998939850302034978 85
UVM_ERROR @ 184266940 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 184266940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 18474047338248664654536322526178943575055374145966805950588528263720507597741 85
UVM_ERROR @ 372683263 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 372683263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
pwrmgr_disable_rom_integrity_check 104774324884490640694555767164244158832822623355841163434264848579807606462463 103
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 96566721285762538769765348379290020717229327869102563275312871799030218317853 99
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 59269014625524386366456730527127886445919862234995716149448289038829459348888 485
UVM_INFO @ 3000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 61161040312888982441262807203949688423439850176591175754985332874920727527817 99
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 45252903926290690648190102425205712807927585600285604256281698632240690919486 116
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 4 test runs
pwrmgr_stress_all 69598897290702827641451840578770559852433335035710824375972007582613270987022 527
UVM_INFO @ 10380525871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 91545100828152185545338000712672920461730242854517006736764818776240229739744 715
UVM_INFO @ 10359377458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 70916673040360036244202771146081222216226984575239252765896577808214190361235 1031
UVM_INFO @ 11420225115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 51455304930653065269584174533702855524981337705030081828245658726319981804627 284
UVM_INFO @ 11073969581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [pwrmgr_common_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all_with_rand_reset 23185618144109762102433453739990763968244677045712984600790063590096053013948 122
UVM_INFO @ 10020343912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitReleaseLcRst 1 test run
pwrmgr_reset_invalid 27870240928248089009201788254613258565457330313190093895275711447881374941754 110
UVM_INFO @ 91024565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitLcInit 1 test run
pwrmgr_reset_invalid 1612053825356825453962917698888923767589583504036337806988351571858735732979 115
UVM_INFO @ 80079427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---