Simulation Results: rom_ctrl/32kb

 
15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.62 %
  • code
  • 92.90 %
  • assert
  • 97.68 %
  • func
  • 99.28 %
  • line
  • 98.94 %
  • branch
  • 98.54 %
  • cond
  • 98.37 %
  • toggle
  • 95.33 %
  • FSM
  • 73.33 %
Validation stages
V1
100.00%
V2
97.18%
V2S
69.49%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 3.150s 756.613us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 3.900s 98.355us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 3.070s 50.709us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.180s 60.297us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.220s 58.088us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.330s 99.067us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 3.070s 50.709us 5 5 100.00
rom_ctrl_csr_aliasing 2.220s 58.088us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 1.990s 52.952us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 1.770s 54.347us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 3.330s 163.510us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 13.170s 752.703us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 2.890s 58.680us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 3.740s 52.458us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 11.700s 718.402us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 11.700s 718.402us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 3.900s 98.355us 1 1 100.00
rom_ctrl_csr_rw 3.070s 50.709us 5 5 100.00
rom_ctrl_csr_aliasing 2.220s 58.088us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.660s 101.334us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 3.900s 98.355us 1 1 100.00
rom_ctrl_csr_rw 3.070s 50.709us 5 5 100.00
rom_ctrl_csr_aliasing 2.220s 58.088us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.660s 101.334us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.115s 0.000us 2 20 10.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 12.430s 2888.256us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 260.350s 1388.014us 5 5 100.00
rom_ctrl_tl_intg_err 59.250s 198.645us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 260.350s 1388.014us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 260.350s 1388.014us 5 5 100.00
sec_cm_checker_ctr_consistency 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.115s 0.000us 2 20 10.00
sec_cm_checker_ctrl_flow_consistency 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.115s 0.000us 2 20 10.00
sec_cm_checker_fsm_local_esc 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.115s 0.000us 2 20 10.00
sec_cm_compare_ctrl_flow_consistency 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.115s 0.000us 2 20 10.00
sec_cm_compare_ctr_consistency 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.115s 0.000us 2 20 10.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 260.350s 1388.014us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 260.350s 1388.014us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 3.150s 756.613us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 3.150s 756.613us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 3.150s 756.613us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 59.250s 198.645us 25 25 100.00
sec_cm_bus_local_esc 4 22 18.18
rom_ctrl_corrupt_sig_fatal_chk 3600.115s 0.000us 2 20 10.00
rom_ctrl_kmac_err_chk 2.890s 58.680us 2 2 100.00
sec_cm_mux_mubi 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.115s 0.000us 2 20 10.00
sec_cm_mux_consistency 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.115s 0.000us 2 20 10.00
sec_cm_ctrl_redun 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.115s 0.000us 2 20 10.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 12.430s 2888.256us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 260.350s 1388.014us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 325.160s 20504.226us 20 20 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 6 test runs
rom_ctrl_corrupt_sig_fatal_chk 104167915463994199786234661450235260118392434425008518302753031865026591865350 None
rom_ctrl_corrupt_sig_fatal_chk 80588681986757902893987300558725949528588696739932604906596688998484122261118 None
rom_ctrl_corrupt_sig_fatal_chk 8154965000307416597902216783675808329883611258899867330504615478366845846734 None
rom_ctrl_corrupt_sig_fatal_chk 16878572072998362508552621791860601356336821824683635045845111264448930311416 None
rom_ctrl_corrupt_sig_fatal_chk 14671393175103070358716177877587918228371027217208606450015630676650120441019 None
rom_ctrl_corrupt_sig_fatal_chk 112167937578265832569028700719022528496475643693587716768969418498266010482035 None
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:301) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.compare_vif.is_waiting()) 4 test runs
rom_ctrl_corrupt_sig_fatal_chk 7956949820462889897877774665139629339855645279419164054017259979639876062818 91
UVM_INFO @ 38645344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 25955282159692375250805214175380050281453563183523961802982751428936676220798 86
UVM_INFO @ 3762237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 30650505942891573264235223883829857806543112961736167251716330579806435951546 84
UVM_INFO @ 5250174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 68211889599812320852254021850897094793638467955160798811416591875050233469046 84
UVM_INFO @ 7364353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:154) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data_o_i.done != MuBi4True) 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 103467356407455497150843005863339749729107278922709487784485781603653663337895 84
UVM_INFO @ 11868385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 23987264430400018071330399521415660959369138198839771002393075798487693547807 99
UVM_INFO @ 1004503080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 98445111802404599029386765655533478891093674231736427398629731881594401367364 96
UVM_INFO @ 18763281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] Expected alert (fatal) did not fire in * cycles. 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 5173291982862947350882493076692531014260053268873565915020016867368088138936 87
UVM_INFO @ 16020740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 60190244977979003648216449567592380743892117865802263348776423887819038733675 90
UVM_INFO @ 354884443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 2166033234539094833406594527863972235725424182119668009209495091233469410431 84
UVM_INFO @ 33663911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 61897535315211575625628533322300596862301581996685490959348185839274883093300 85
UVM_INFO @ 680591933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 105856914699537224141846357245432793763008415833924776975455334002043419081389 85
UVM_INFO @ 163510326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:284) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.fsm_vif.get_fsm_state() == rom_ctrl_pkg::ReadingLow) 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 1886681673688316214931423426406035066546090843020356295919910790441101047289 93
UVM_INFO @ 1697221422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 18264162477580412274000277767052730942142611373908037043580700290017167599370 84
UVM_INFO @ 36433072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---