Simulation Results: rom_ctrl/64kb

 
15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.97 %
  • code
  • 97.10 %
  • assert
  • 97.53 %
  • func
  • 99.28 %
  • line
  • 99.07 %
  • branch
  • 99.27 %
  • cond
  • 98.51 %
  • toggle
  • 95.34 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
97.18%
V2S
69.49%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 11.780s 1393.419us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.370s 61.739us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 4.900s 51.127us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.310s 111.916us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.870s 90.262us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.450s 64.794us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 4.900s 51.127us 5 5 100.00
rom_ctrl_csr_aliasing 4.870s 90.262us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.380s 59.538us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.540s 50.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 5.730s 330.854us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 27.380s 1459.786us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 10.380s 2400.434us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 5.850s 57.338us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 14.510s 352.520us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 14.510s 352.520us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 7.370s 61.739us 1 1 100.00
rom_ctrl_csr_rw 4.900s 51.127us 5 5 100.00
rom_ctrl_csr_aliasing 4.870s 90.262us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.710s 355.218us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 7.370s 61.739us 1 1 100.00
rom_ctrl_csr_rw 4.900s 51.127us 5 5 100.00
rom_ctrl_csr_aliasing 4.870s 90.262us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.710s 355.218us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.121s 0.000us 2 20 10.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.720s 231.082us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 539.800s 724.299us 5 5 100.00
rom_ctrl_tl_intg_err 146.990s 552.339us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 539.800s 724.299us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 539.800s 724.299us 5 5 100.00
sec_cm_checker_ctr_consistency 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.121s 0.000us 2 20 10.00
sec_cm_checker_ctrl_flow_consistency 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.121s 0.000us 2 20 10.00
sec_cm_checker_fsm_local_esc 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.121s 0.000us 2 20 10.00
sec_cm_compare_ctrl_flow_consistency 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.121s 0.000us 2 20 10.00
sec_cm_compare_ctr_consistency 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.121s 0.000us 2 20 10.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 539.800s 724.299us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 539.800s 724.299us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 11.780s 1393.419us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 11.780s 1393.419us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 11.780s 1393.419us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 146.990s 552.339us 25 25 100.00
sec_cm_bus_local_esc 4 22 18.18
rom_ctrl_corrupt_sig_fatal_chk 3600.121s 0.000us 2 20 10.00
rom_ctrl_kmac_err_chk 10.380s 2400.434us 2 2 100.00
sec_cm_mux_mubi 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.121s 0.000us 2 20 10.00
sec_cm_mux_consistency 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.121s 0.000us 2 20 10.00
sec_cm_ctrl_redun 2 20 10.00
rom_ctrl_corrupt_sig_fatal_chk 3600.121s 0.000us 2 20 10.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.720s 231.082us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 539.800s 724.299us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 260.760s 32227.730us 20 20 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
rom_ctrl_corrupt_sig_fatal_chk 99805456119962042526160414254120940056433328624200897329381603607373686164009 None
rom_ctrl_corrupt_sig_fatal_chk 56512124714639386472093053752153111548787618346413009494615344845856367495184 None
rom_ctrl_corrupt_sig_fatal_chk 60245687466150433432049203446166665747252297747062656092546680009945377326938 None
rom_ctrl_corrupt_sig_fatal_chk 23121070154326724244065479373218579703319713459748028928535180780951702263844 None
rom_ctrl_corrupt_sig_fatal_chk 24234042696842114047241679772467406673970827348886595008138630312968292649448 None
rom_ctrl_corrupt_sig_fatal_chk 70608433268414291917228067301418179017652068419765618248919173026430392360192 None
rom_ctrl_corrupt_sig_fatal_chk 30836744668542454962262285428991178653863811936996607017687861762009545653512 None
rom_ctrl_corrupt_sig_fatal_chk 39518910001406013286478555090000538946858011481495443353234394310334596119598 None
rom_ctrl_corrupt_sig_fatal_chk 693427204211051535998597937510058438146324151253731718440740447936470809773 None
rom_ctrl_corrupt_sig_fatal_chk 96801198963380291057257869760470214415249512125897586729392004236955718251738 None
rom_ctrl_corrupt_sig_fatal_chk 113287032162581574986995647146688503206651159267235197973965815668159062383470 None
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:301) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.compare_vif.is_waiting()) 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 97385816617654205704031497496849216053606844767210461875791155598273613967006 93
UVM_INFO @ 57882103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 67080669664123191892114519270567849615497146818160165499273140328846019414128 84
UVM_INFO @ 8625020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 104757886068386999663778279563623172483915337353594550626674922237039547838521 84
UVM_INFO @ 10600050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 115283493597868823575604609232975156787180714913665964072512486741379239625354 85
UVM_INFO @ 330853901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 73708523714387916466485634697079806059891079146682810424935990766198385086432 85
UVM_INFO @ 28496451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:154) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data_o_i.done != MuBi4True) 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 56468953212998548830022590581091293826154905356832576907954741821250797480574 84
UVM_INFO @ 2533958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 29908246088602199934849254617656436533724320673750350527203810566774327857797 84
UVM_INFO @ 8327742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:284) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.fsm_vif.get_fsm_state() == rom_ctrl_pkg::ReadingLow) 1 test run
rom_ctrl_corrupt_sig_fatal_chk 77585099777848240299573773206014379706555538111299441750136107309809293812976 101
UVM_INFO @ 7679682768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [rom_ctrl_corrupt_sig_fatal_chk_vseq] Expected alert (fatal) did not fire in * cycles. 1 test run
rom_ctrl_corrupt_sig_fatal_chk 29400327631513687342235205923369452823039284771309292465991420150756924382169 95
UVM_INFO @ 470892185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---