| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| rstmgr_smoke | 1.840s | 265.208us | 5 | 5 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.150s | 106.695us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rstmgr_csr_rw | 1.180s | 96.327us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rstmgr_csr_bit_bash | 11.180s | 2467.549us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rstmgr_csr_aliasing | 2.210s | 253.001us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rstmgr_csr_mem_rw_with_rand_reset | 1.780s | 219.193us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rstmgr_csr_rw | 1.180s | 96.327us | 5 | 5 | 100.00 | |
| rstmgr_csr_aliasing | 2.210s | 253.001us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_stretcher | 5 | 5 | 100.00 | |||
| rstmgr_por_stretcher | 1.240s | 193.238us | 5 | 5 | 100.00 | |
| sw_rst | 5 | 5 | 100.00 | |||
| rstmgr_sw_rst | 2.910s | 569.245us | 5 | 5 | 100.00 | |
| sw_rst_reset_race | 5 | 5 | 100.00 | |||
| rstmgr_sw_rst_reset_race | 1.460s | 166.568us | 5 | 5 | 100.00 | |
| reset_info | 5 | 5 | 100.00 | |||
| rstmgr_reset | 8.060s | 2251.804us | 5 | 5 | 100.00 | |
| cpu_info | 5 | 5 | 100.00 | |||
| rstmgr_reset | 8.060s | 2251.804us | 5 | 5 | 100.00 | |
| alert_info | 5 | 5 | 100.00 | |||
| rstmgr_reset | 8.060s | 2251.804us | 5 | 5 | 100.00 | |
| reset_info_capture | 5 | 5 | 100.00 | |||
| rstmgr_reset | 8.060s | 2251.804us | 5 | 5 | 100.00 | |
| stress_all | 5 | 5 | 100.00 | |||
| rstmgr_stress_all | 38.870s | 11978.117us | 5 | 5 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rstmgr_alert_test | 1.130s | 71.497us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rstmgr_tl_errors | 3.950s | 523.834us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rstmgr_tl_errors | 3.950s | 523.834us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.150s | 106.695us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 1.180s | 96.327us | 5 | 5 | 100.00 | |
| rstmgr_csr_aliasing | 2.210s | 253.001us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 2.070s | 252.292us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rstmgr_csr_hw_reset | 1.150s | 106.695us | 1 | 1 | 100.00 | |
| rstmgr_csr_rw | 1.180s | 96.327us | 5 | 5 | 100.00 | |
| rstmgr_csr_aliasing | 2.210s | 253.001us | 1 | 1 | 100.00 | |
| rstmgr_same_csr_outstanding | 2.070s | 252.292us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rstmgr_sec_cm | 26.060s | 16894.834us | 5 | 5 | 100.00 | |
| rstmgr_tl_intg_err | 4.130s | 914.996us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm | 26.060s | 16894.834us | 5 | 5 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm | 26.060s | 16894.834us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rstmgr_tl_intg_err | 4.130s | 914.996us | 25 | 25 | 100.00 | |
| sec_cm_scan_intersig_mubi | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm_scan_intersig_mubi | 1.690s | 202.659us | 5 | 5 | 100.00 | |
| sec_cm_leaf_rst_bkgn_chk | 25 | 25 | 100.00 | |||
| rstmgr_leaf_rst_cnsty | 9.690s | 2799.302us | 25 | 25 | 100.00 | |
| sec_cm_leaf_rst_shadow | 5 | 5 | 100.00 | |||
| rstmgr_leaf_rst_shadow_attack | 1.690s | 302.690us | 5 | 5 | 100.00 | |
| sec_cm_leaf_fsm_sparse | 5 | 5 | 100.00 | |||
| rstmgr_sec_cm | 26.060s | 16894.834us | 5 | 5 | 100.00 | |
| sec_cm_sw_rst_config_regwen | 5 | 5 | 100.00 | |||
| rstmgr_csr_rw | 1.180s | 96.327us | 5 | 5 | 100.00 | |
| sec_cm_dump_ctrl_config_regwen | 5 | 5 | 100.00 | |||
| rstmgr_csr_rw | 1.180s | 96.327us | 5 | 5 | 100.00 | |