Simulation Results: rv_timer

 
15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.08 %
  • code
  • 94.66 %
  • assert
  • 97.77 %
  • func
  • 98.82 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
99.21%
V2S
100.00%
V3
52.50%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 1.670s 840.782us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.820s 17.809us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 0.850s 56.352us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.210s 879.075us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.940s 37.701us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.130s 102.699us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 0.850s 56.352us 5 5 100.00
rv_timer_csr_aliasing 0.940s 37.701us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 20 20 100.00
rv_timer_random_reset 5.310s 21553.437us 20 20 100.00
disabled 20 20 100.00
rv_timer_disabled 2.990s 2163.610us 20 20 100.00
cfg_update_on_fly 9 10 90.00
rv_timer_cfg_update_on_fly 1640.780s 10000000.000us 9 10 90.00
no_interrupt_test 9 10 90.00
rv_timer_cfg_update_on_fly 1640.780s 10000000.000us 9 10 90.00
stress 20 20 100.00
rv_timer_stress_all 7.830s 11400.446us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 0.890s 42.586us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 0.840s 23.044us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 2.690s 106.767us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 2.690s 106.767us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 0.820s 17.809us 1 1 100.00
rv_timer_csr_rw 0.850s 56.352us 5 5 100.00
rv_timer_csr_aliasing 0.940s 37.701us 1 1 100.00
rv_timer_same_csr_outstanding 1.070s 37.722us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 0.820s 17.809us 1 1 100.00
rv_timer_csr_rw 0.850s 56.352us 5 5 100.00
rv_timer_csr_aliasing 0.940s 37.701us 1 1 100.00
rv_timer_same_csr_outstanding 1.070s 37.722us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 1.260s 88.590us 5 5 100.00
rv_timer_tl_intg_err 1.580s 530.925us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 1.580s 530.925us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 10 10.00
rv_timer_min 2.130s 234.935us 1 10 10.00
max_value 0 10 0.00
rv_timer_max 1.770s 906.990us 0 10 0.00
stress_all_with_rand_reset 20 20 100.00
rv_timer_stress_all_with_rand_reset 57.530s 25490.781us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 10 test runs
rv_timer_max 48900233577268901665692279161562832009496799798197198092091113420957830111575 81
UVM_INFO @ 153191083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 95686741638167571918958106756993560038820432796268967160085489215460283220601 81
UVM_INFO @ 181256805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 59937543525673350930433995831955528627899544713459697319719164862702855250042 81
UVM_INFO @ 153149114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 60602290601009503200003738742343165433399836192883321229827702035226528612088 81
UVM_INFO @ 382862204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 16641981957411031956899781200338243050057642329869045156092461567416933027000 81
UVM_INFO @ 241567980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 775186632147654988285981749712056161966733110203311646479674126139565998481 81
UVM_INFO @ 45194283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 56506848709099723617604904572065687646403780100504018238760352835661374796697 81
UVM_INFO @ 177813365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 91036167033123079550523435205250790270959159804824770720767958121163704699160 81
UVM_INFO @ 45477543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 113834272257460748329277482201298250242097425146436989028956922391641345374909 81
UVM_INFO @ 906989720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 78300543834734463613932304462796898271998768496931519518985914187930566863947 81
UVM_INFO @ 178159837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 9 test runs
rv_timer_min 42782327285229767924947477863870479111180741528072553985991253523656431804241 83
UVM_INFO @ 234934871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 17949989139062279173798201099434264629038596511679893508314630082802562975705 83
UVM_INFO @ 233728040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 105183824892433117853839509569014863972702944198655936990650596789594158838041 81
UVM_INFO @ 146144421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 115252322925544957589822845693564570750496199672294058681778211305423775025623 81
UVM_INFO @ 72645437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 8978861126114086666867303664264484091527621681384466375053675171393194370127 82
UVM_INFO @ 71713149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 36426426902176223608903160345899071611570567743576955433279780918910703345715 84
UVM_INFO @ 59842784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 42262109952703417178425399504036245978263302659238690200133068003128112905142 81
UVM_INFO @ 478483606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 61208122673895004895527586236176480238840647418285500348746479621689380135586 81
UVM_INFO @ 79431284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 24815197738474433280499470258408563297986503502686062491554615888904666635857 82
UVM_INFO @ 71552763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rv_timer_cfg_update_on_fly 34775309942767384815714657502152665079965240738058511033024063345802950864391 114
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---