Simulation Results: spi_host

 
15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.95 %
  • code
  • 91.30 %
  • assert
  • 96.79 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 53.000s 24956.105us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 32.844us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 1.000s 30.545us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 291.114us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 69.138us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 26.657us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 1.000s 30.545us 5 5 100.00
spi_host_csr_aliasing 1.000s 69.138us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 36.661us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 31.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 187.352us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 11.000s 964.673us 10 10 100.00
spi_host_error_cmd 2.000s 48.203us 10 10 100.00
spi_host_event 17.000s 842.190us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 5.000s 1533.058us 10 10 100.00
speed 10 10 100.00
spi_host_speed 5.000s 1533.058us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 5.000s 1533.058us 10 10 100.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 407.000s 30256.807us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 72.000s 6254.254us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 77.336us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 5.000s 1533.058us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 5.000s 1533.058us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 53.000s 24956.105us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 53.000s 24956.105us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 18.000s 662.972us 10 10 100.00
spien 10 10 100.00
spi_host_spien 74.000s 5625.556us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 1851.000s 857507.126us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 3.000s 99.649us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 11.000s 964.673us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 3.000s 18.239us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 14.623us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 595.417us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 595.417us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 32.844us 1 1 100.00
spi_host_csr_rw 1.000s 30.545us 5 5 100.00
spi_host_csr_aliasing 1.000s 69.138us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 40.089us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 32.844us 1 1 100.00
spi_host_csr_rw 1.000s 30.545us 5 5 100.00
spi_host_csr_aliasing 1.000s 69.138us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 40.089us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 2.000s 66.872us 25 25 100.00
spi_host_sec_cm 2.000s 345.139us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 2.000s 66.872us 25 25 100.00