Simulation Results: sysrst_ctrl

 
15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.23 %
  • code
  • 98.32 %
  • assert
  • 98.75 %
  • func
  • 85.61 %
  • line
  • 99.37 %
  • branch
  • 99.44 %
  • cond
  • 97.93 %
  • toggle
  • 100.00 %
  • FSM
  • 94.87 %
Validation stages
V1
100.00%
V2
98.20%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
sysrst_ctrl_smoke 7.000s 2112.906us 10 10 100.00
input_output_inverted 10 10 100.00
sysrst_ctrl_in_out_inverted 8.300s 2467.781us 10 10 100.00
combo_detect_ec_rst 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst 7.990s 2390.462us 5 5 100.00
combo_detect_ec_rst_with_pre_cond 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 8.720s 2528.039us 5 5 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.790s 4037.530us 1 1 100.00
csr_rw 5 5 100.00
sysrst_ctrl_csr_rw 5.680s 2031.789us 5 5 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 14.860s 6067.210us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 6.250s 3016.632us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 7.190s 2084.401us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sysrst_ctrl_csr_rw 5.680s 2031.789us 5 5 100.00
sysrst_ctrl_csr_aliasing 6.250s 3016.632us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 25 25 100.00
sysrst_ctrl_combo_detect 327.480s 159655.061us 25 25 100.00
combo_detect_with_pre_cond 97 100 97.00
sysrst_ctrl_combo_detect_with_pre_cond 380.360s 200822.524us 97 100 97.00
auto_block_key_outputs 25 25 100.00
sysrst_ctrl_auto_blk_key_output 183.400s 145527.385us 25 25 100.00
keyboard_input_triggered_interrupt 50 50 100.00
sysrst_ctrl_edge_detect 691.770s 1092494.488us 50 50 100.00
pin_output_keyboard_inversion_control 10 10 100.00
sysrst_ctrl_pin_override_test 8.940s 2513.923us 10 10 100.00
pin_input_value_accessibility 10 10 100.00
sysrst_ctrl_pin_access_test 7.470s 2252.122us 10 10 100.00
ec_power_on_reset 10 10 100.00
sysrst_ctrl_ec_pwr_on_rst 168.890s 181416.145us 10 10 100.00
flash_write_protect_output 10 10 100.00
sysrst_ctrl_flash_wr_prot_out 8.490s 2614.859us 10 10 100.00
ultra_low_power_test 23 25 92.00
sysrst_ctrl_ultra_low_pwr 617.150s 2195339.046us 23 25 92.00
sysrst_ctrl_feature_disable 2 2 100.00
sysrst_ctrl_feature_disable 44.380s 39326.600us 2 2 100.00
stress_all 9 10 90.00
sysrst_ctrl_stress_all 243.540s 128168.780us 9 10 90.00
alert_test 10 10 100.00
sysrst_ctrl_alert_test 7.260s 2012.650us 10 10 100.00
intr_test 10 10 100.00
sysrst_ctrl_intr_test 6.780s 2014.855us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sysrst_ctrl_tl_errors 8.300s 2074.736us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sysrst_ctrl_tl_errors 8.300s 2074.736us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sysrst_ctrl_csr_hw_reset 3.790s 4037.530us 1 1 100.00
sysrst_ctrl_csr_rw 5.680s 2031.789us 5 5 100.00
sysrst_ctrl_csr_aliasing 6.250s 3016.632us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 24.220s 7832.395us 5 5 100.00
tl_d_partial_access 12 12 100.00
sysrst_ctrl_csr_hw_reset 3.790s 4037.530us 1 1 100.00
sysrst_ctrl_csr_rw 5.680s 2031.789us 5 5 100.00
sysrst_ctrl_csr_aliasing 6.250s 3016.632us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 24.220s 7832.395us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
sysrst_ctrl_sec_cm 81.190s 42008.082us 5 5 100.00
sysrst_ctrl_tl_intg_err 92.760s 42487.168us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
sysrst_ctrl_tl_intg_err 92.760s 42487.168us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
sysrst_ctrl_stress_all_with_rand_reset 15.760s 5610.864us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)  3 test runs
sysrst_ctrl_stress_all 114943024580149630473068616569414902590274262185724976551990386227422351627175 672
UVM_INFO @ 15717830170 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
UVM_INFO @ 17032830170 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 17062795942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 38438905775829723909899298918663719967097776157014425271316009501369453411211 661
UVM_ERROR @ 5657136050 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 5657136050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 66287954671726499161472526590689626871844302784205520226641894957342909478568 661
UVM_ERROR @ 4439532732 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 4439532732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) 2 test runs
sysrst_ctrl_combo_detect_with_pre_cond 103440014818917539046795060518021102330447199312325019856678739988308372322772 691
UVM_ERROR @ 35586602486 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 35586602486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_combo_detect_with_pre_cond 80744815595371595685928301897536790351038667107588487529919872411519685517808 675
UVM_ERROR @ 13605525501 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 13605525501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 17376814867533111064048174446288794231325898773059297892140098981809079683140 742
UVM_ERROR @ 107705516005 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 107705516005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---