Simulation Results

Simulation Results: uart

15/08/2026 02:51:09 DVSim: v1.49.0 sha: e6fb888 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.91 %

code
92.64 %

assert
98.85 %

func
99.23 %

line
99.48 %

branch
98.14 %

cond
98.25 %

toggle
74.67 %

Validation stages

V1		100.00%
V2		96.98%
V2S		100.00%
V3		85.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	uart_smoke	15.740s	5472.055us	10	10	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.850s	46.600us	1	1	100.00
csr_rw				5	5	100.00
	uart_csr_rw	0.940s	18.152us	5	5	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	2.660s	84.081us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.980s	166.424us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	uart_csr_mem_rw_with_rand_reset	1.210s	123.068us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	uart_csr_rw	0.940s	18.152us	5	5	100.00
	uart_csr_aliasing	0.980s	166.424us	1	1	100.00

385/397 passed

96.98 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				10	10	100.00
	uart_tx_rx	76.230s	87964.478us	10	10	100.00
parity				20	20	100.00
	uart_smoke	15.740s	5472.055us	10	10	100.00
	uart_tx_rx	76.230s	87964.478us	10	10	100.00
parity_error				20	20	100.00
	uart_intr	115.910s	158243.631us	10	10	100.00
	uart_rx_parity_err	199.850s	131477.217us	10	10	100.00
watermark				20	20	100.00
	uart_tx_rx	76.230s	87964.478us	10	10	100.00
	uart_intr	115.910s	158243.631us	10	10	100.00
fifo_full				10	10	100.00
	uart_fifo_full	143.570s	121432.345us	10	10	100.00
fifo_overflow				10	10	100.00
	uart_fifo_overflow	141.120s	132870.803us	10	10	100.00
fifo_reset				200	200	100.00
	uart_fifo_reset	285.980s	222910.648us	200	200	100.00
rx_frame_err				10	10	100.00
	uart_intr	115.910s	158243.631us	10	10	100.00
rx_break_err				10	10	100.00
	uart_intr	115.910s	158243.631us	10	10	100.00
rx_timeout				10	10	100.00
	uart_intr	115.910s	158243.631us	10	10	100.00
perf				10	10	100.00
	uart_perf	504.440s	20962.506us	10	10	100.00
sys_loopback				10	10	100.00
	uart_loopback	16.360s	4915.067us	10	10	100.00
line_loopback				10	10	100.00
	uart_loopback	16.360s	4915.067us	10	10	100.00
rx_noise_filter				1	10	10.00
	uart_noise_filter	46.300s	46389.932us	1	10	10.00
rx_start_bit_filter				10	10	100.00
	uart_rx_start_bit_filter	31.940s	37695.575us	10	10	100.00
tx_overide				10	10	100.00
	uart_tx_ovrd	21.040s	6668.433us	10	10	100.00
rx_oversample				10	10	100.00
	uart_rx_oversample	32.780s	5890.380us	10	10	100.00
long_b2b_transfer				10	10	100.00
	uart_long_xfer_wo_dly	585.250s	123682.854us	10	10	100.00
stress_all				7	10	70.00
	uart_stress_all	195.770s	164941.194us	7	10	70.00
alert_test				10	10	100.00
	uart_alert_test	0.940s	53.801us	10	10	100.00
intr_test				10	10	100.00
	uart_intr_test	0.940s	11.467us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	uart_tl_errors	2.360s	139.243us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	uart_tl_errors	2.360s	139.243us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	uart_csr_hw_reset	0.850s	46.600us	1	1	100.00
	uart_csr_rw	0.940s	18.152us	5	5	100.00
	uart_csr_aliasing	0.980s	166.424us	1	1	100.00
	uart_same_csr_outstanding	1.150s	119.109us	5	5	100.00
tl_d_partial_access				12	12	100.00
	uart_csr_hw_reset	0.850s	46.600us	1	1	100.00
	uart_csr_rw	0.940s	18.152us	5	5	100.00
	uart_csr_aliasing	0.980s	166.424us	1	1	100.00
	uart_same_csr_outstanding	1.150s	119.109us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	uart_sec_cm	1.260s	337.403us	5	5	100.00
	uart_tl_intg_err	2.000s	1637.571us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	uart_tl_intg_err	2.000s	1637.571us	25	25	100.00

17/20 passed

85.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				17	20	85.00
	uart_stress_all_with_rand_reset	63.550s	8799.348us	17	20	85.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:390) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				6 test runs
	uart_noise_filter	100952959172045628156372633130283355495678929679786602124552558299711387536622	80	UVM_ERROR @ 212419895 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 264975398 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1 UVM_ERROR @ 264975398 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 753530465 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 4, clk_pulses: 0
	uart_noise_filter	102577184210059562182200109165655882382054114573491799823168581947077174716795	83	UVM_ERROR @ 45234145445 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 45234145445 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 46380174602 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1 UVM_ERROR @ 46380174602 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_noise_filter	7328017601336640153770487251783586270109292719307192329689775897474123111058	82	UVM_ERROR @ 1545664185 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 1546714185 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 1547834185 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 1548924185 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_stress_all	45461355102774249749933214357338323704169052101380883587350515026135213803283	95	UVM_ERROR @ 14322161664 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_INFO @ 15583761664 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 5/14 UVM_INFO @ 30753961664 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 6/14 UVM_INFO @ 31291921664 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 7/14
	uart_noise_filter	62548245796442495881525285202044096779002347912647763857315726612336682061801	80	UVM_ERROR @ 71410552 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 1476501352 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 1476501352 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 2681206000 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_stress_all_with_rand_reset	68567212042887634968056947711326602672083993495573504000584428852923448215652	116	UVM_ERROR @ 3933812288 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 3934452288 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 3935052288 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 3935412288 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:				6 test runs
	uart_noise_filter	96019216576449425766072567696435487423437997847810324058047894697398906622741	87	UVM_ERROR @ 69220218009 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 69220252492 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (134 [0x86] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 69220321458 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 69220355941 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (134 [0x86] vs 187 [0xbb]) reg name: uart_reg_block.rdata
	uart_stress_all	95980536149309354877579092525443145340834773894596856640757110767150833159478	85	UVM_ERROR @ 36685258487 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 36685306106 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 36685401344 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 36685448963 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
	uart_noise_filter	89248772917754174402099251571263761901804205242425453042731585731775496049518	82	UVM_ERROR @ 4532532178 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 4532552178 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (237 [0xed] vs 251 [0xfb]) reg name: uart_reg_block.rdata UVM_ERROR @ 4605792178 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6, clk_pulses: 0 UVM_ERROR @ 4605832178 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_stress_all	101023814964145668896973398102929962557294633546212882342616933395675624282087	92	UVM_ERROR @ 33113887481 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 33113897481 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (214 [0xd6] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 33314287481 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0 UVM_ERROR @ 33314307481 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_noise_filter	38119594642284409506867588917494634311419123378601206053585898877126593212860	81	UVM_ERROR @ 39191568475 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 39191610142 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (175 [0xaf] vs 127 [0x7f]) reg name: uart_reg_block.rdata UVM_ERROR @ 39423403663 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0 UVM_ERROR @ 39423486997 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_noise_filter	28072529156019917697650560767230257335312554033827922917344019474694712322248	83	UVM_ERROR @ 9860633478 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 9860735518 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata UVM_ERROR @ 10200957286 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 10200957286 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [] vs []) check rx_empty fail: uart_rx_clk_pulses = , rx_q.size = *				1 test run
	uart_noise_filter	105816899557709656221500079708653368026717923549354661906530418302656570456283	83	UVM_ERROR @ 7952497458 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 7952497458 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 8234453202 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 2 (+/-1), act: 12, clk_pulses: 0 UVM_ERROR @ 8234522970 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (22 [0x16] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR (cip_base_vseq.sv:1296) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	uart_stress_all_with_rand_reset	91019400236624303223301745592437490307427809534785600169842633689329903545835	194	UVM_ERROR @ 7211613853 ps: (cip_base_vseq.sv:1209) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. UVM_INFO @ 7211613853 ps: (cip_base_vseq.sv:1213) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Issuing reset for run 8/10 UVM_INFO @ 7211623144 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1
UVM_ERROR (cip_base_vseq.sv:1209) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.				1 test run
	uart_stress_all_with_rand_reset	38023160072135952389991424912372811953885328712427768387406355634896629075284	114	UVM_INFO @ 2004815277 ps: (cip_base_vseq.sv:1213) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Issuing reset for run 4/10 UVM_INFO @ 2005027398 ps: (cip_base_vseq.sv:1233) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Stress w/ reset is done for run 4/10