Simulation Results: adc_ctrl

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.62 %
  • code
  • 98.54 %
  • assert
  • 96.92 %
  • func
  • 19.39 %
  • line
  • 99.05 %
  • branch
  • 98.51 %
  • cond
  • 95.12 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
adc_ctrl_smoke 18.610s 5979.667us 10 10 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.180s 877.380us 1 1 100.00
csr_rw 5 5 100.00
adc_ctrl_csr_rw 2.120s 472.565us 5 5 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 15.670s 18391.338us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.720s 994.626us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 2.340s 428.239us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
adc_ctrl_csr_rw 2.120s 472.565us 5 5 100.00
adc_ctrl_csr_aliasing 1.720s 994.626us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 10 10 100.00
adc_ctrl_filters_polled 47.230s 19735.976us 10 10 100.00
filters_polled_fixed 10 10 100.00
adc_ctrl_filters_polled_fixed 98.330s 54178.832us 10 10 100.00
filters_interrupt 10 10 100.00
adc_ctrl_filters_interrupt 137.060s 56154.402us 10 10 100.00
filters_interrupt_fixed 10 10 100.00
adc_ctrl_filters_interrupt_fixed 133.940s 49632.584us 10 10 100.00
filters_wakeup 10 10 100.00
adc_ctrl_filters_wakeup 151.270s 72760.608us 10 10 100.00
filters_wakeup_fixed 10 10 100.00
adc_ctrl_filters_wakeup_fixed 144.320s 77008.600us 10 10 100.00
filters_both 10 10 100.00
adc_ctrl_filters_both 162.550s 68361.614us 10 10 100.00
clock_gating 10 10 100.00
adc_ctrl_clock_gating 87.800s 71888.507us 10 10 100.00
poweron_counter 10 10 100.00
adc_ctrl_poweron_counter 13.140s 4494.619us 10 10 100.00
lowpower_counter 10 10 100.00
adc_ctrl_lowpower_counter 89.740s 40700.316us 10 10 100.00
fsm_reset 10 10 100.00
adc_ctrl_fsm_reset 296.880s 110383.734us 10 10 100.00
stress_all 10 10 100.00
adc_ctrl_stress_all 806.430s 336352.165us 10 10 100.00
alert_test 10 10 100.00
adc_ctrl_alert_test 2.280s 521.877us 10 10 100.00
intr_test 10 10 100.00
adc_ctrl_intr_test 2.410s 523.451us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
adc_ctrl_tl_errors 4.250s 421.575us 25 25 100.00
tl_d_illegal_access 25 25 100.00
adc_ctrl_tl_errors 4.250s 421.575us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
adc_ctrl_csr_hw_reset 2.180s 877.380us 1 1 100.00
adc_ctrl_csr_rw 2.120s 472.565us 5 5 100.00
adc_ctrl_csr_aliasing 1.720s 994.626us 1 1 100.00
adc_ctrl_same_csr_outstanding 11.620s 4779.538us 5 5 100.00
tl_d_partial_access 12 12 100.00
adc_ctrl_csr_hw_reset 2.180s 877.380us 1 1 100.00
adc_ctrl_csr_rw 2.120s 472.565us 5 5 100.00
adc_ctrl_csr_aliasing 1.720s 994.626us 1 1 100.00
adc_ctrl_same_csr_outstanding 11.620s 4779.538us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
adc_ctrl_sec_cm 20.070s 8221.372us 5 5 100.00
adc_ctrl_tl_intg_err 21.020s 8940.245us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
adc_ctrl_tl_intg_err 21.020s 8940.245us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
adc_ctrl_stress_all_with_rand_reset 16.850s 11776.455us 9 10 90.00

Error Messages

   Test seed line log context
Offending '(np_sample_cnt_q == '0)' 1 test run
adc_ctrl_stress_all_with_rand_reset 105564335708123293613331826687457404314858257724408325335819755080422912820625 448
UVM_ERROR @ 1440748323 ps: (adc_ctrl_fsm.sv:386) [ASSERT FAILED] NpCntClrPwrDn_A
UVM_INFO @ 1440748323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---