Simulation Results

Simulation Results: clkmgr

22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
94.19 %

code
98.85 %

assert
95.90 %

func
87.82 %

line
99.29 %

branch
99.06 %

cond
95.89 %

toggle
100.00 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		100.00%
V2S		75.17%
V3		100.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	2.060s	234.230us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.160s	27.639us	1	1	100.00
csr_rw				5	5	100.00
	clkmgr_csr_rw	1.100s	29.331us	5	5	100.00
csr_bit_bash				1	1	100.00
	clkmgr_csr_bit_bash	12.300s	1096.084us	1	1	100.00
csr_aliasing				1	1	100.00
	clkmgr_csr_aliasing	1.510s	39.651us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	clkmgr_csr_mem_rw_with_rand_reset	2.230s	128.026us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	clkmgr_csr_rw	1.100s	29.331us	5	5	100.00
	clkmgr_csr_aliasing	1.510s	39.651us	1	1	100.00

127/127 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	1.390s	122.079us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	1.720s	144.747us	10	10	100.00
extclk				10	10	100.00
	clkmgr_extclk	2.220s	345.690us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	1.090s	16.823us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	2.060s	234.230us	10	10	100.00
frequency				10	10	100.00
	clkmgr_frequency	14.520s	2021.617us	10	10	100.00
frequency_timeout				10	10	100.00
	clkmgr_frequency_timeout	14.660s	1817.620us	10	10	100.00
frequency_overflow				10	10	100.00
	clkmgr_frequency	14.520s	2021.617us	10	10	100.00
stress_all				10	10	100.00
	clkmgr_stress_all	49.530s	12012.491us	10	10	100.00
alert_test				10	10	100.00
	clkmgr_alert_test	1.350s	84.757us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	4.810s	426.267us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	4.810s	426.267us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	clkmgr_csr_hw_reset	1.160s	27.639us	1	1	100.00
	clkmgr_csr_rw	1.100s	29.331us	5	5	100.00
	clkmgr_csr_aliasing	1.510s	39.651us	1	1	100.00
	clkmgr_same_csr_outstanding	2.090s	120.965us	5	5	100.00
tl_d_partial_access				12	12	100.00
	clkmgr_csr_hw_reset	1.160s	27.639us	1	1	100.00
	clkmgr_csr_rw	1.100s	29.331us	5	5	100.00
	clkmgr_csr_aliasing	1.510s	39.651us	1	1	100.00
	clkmgr_same_csr_outstanding	2.090s	120.965us	5	5	100.00

V2S

109/145 passed

75.17 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				13	30	43.33
	clkmgr_sec_cm	66.130s	10155.598us	1	5	20.00
	clkmgr_tl_intg_err	74.820s	10030.560us	12	25	48.00
shadow_reg_update_error				11	20	55.00
	clkmgr_shadow_reg_errors	1437.900s	200000.000us	11	20	55.00
shadow_reg_read_clear_staged_value				11	20	55.00
	clkmgr_shadow_reg_errors	1437.900s	200000.000us	11	20	55.00
shadow_reg_storage_error				11	20	55.00
	clkmgr_shadow_reg_errors	1437.900s	200000.000us	11	20	55.00
shadowed_reset_glitch				11	20	55.00
	clkmgr_shadow_reg_errors	1437.900s	200000.000us	11	20	55.00
shadow_reg_update_error_with_csr_rw				10	20	50.00
	clkmgr_shadow_reg_errors_with_csr_rw	803.690s	200000.000us	10	20	50.00
sec_cm_bus_integrity				12	25	48.00
	clkmgr_tl_intg_err	74.820s	10030.560us	12	25	48.00
sec_cm_meas_clk_bkgn_chk				10	10	100.00
	clkmgr_frequency	14.520s	2021.617us	10	10	100.00
sec_cm_timeout_clk_bkgn_chk				10	10	100.00
	clkmgr_frequency_timeout	14.660s	1817.620us	10	10	100.00
sec_cm_meas_config_shadow				11	20	55.00
	clkmgr_shadow_reg_errors	1437.900s	200000.000us	11	20	55.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	1.590s	86.828us	10	10	100.00
sec_cm_lc_ctrl_intersig_mubi				10	10	100.00
	clkmgr_lc_ctrl_intersig_mubi	2.010s	275.318us	10	10	100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi				10	10	100.00
	clkmgr_lc_clk_byp_req_intersig_mubi	1.390s	86.228us	10	10	100.00
sec_cm_clk_handshake_intersig_mubi				10	10	100.00
	clkmgr_clk_handshake_intersig_mubi	1.570s	134.646us	10	10	100.00
sec_cm_div_intersig_mubi				10	10	100.00
	clkmgr_div_intersig_mubi	1.380s	91.309us	10	10	100.00
sec_cm_jitter_config_mubi				5	5	100.00
	clkmgr_csr_rw	1.100s	29.331us	5	5	100.00
sec_cm_idle_ctr_redun				1	5	20.00
	clkmgr_sec_cm	66.130s	10155.598us	1	5	20.00
sec_cm_meas_config_regwen				5	5	100.00
	clkmgr_csr_rw	1.100s	29.331us	5	5	100.00
sec_cm_clk_ctrl_config_regwen				5	5	100.00
	clkmgr_csr_rw	1.100s	29.331us	5	5	100.00
prim_count_check				1	5	20.00
	clkmgr_sec_cm	66.130s	10155.598us	1	5	20.00

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
regwen				10	10	100.00
	clkmgr_regwen	9.250s	1200.780us	10	10	100.00
stress_all_with_rand_reset				10	10	100.00
	clkmgr_stress_all_with_rand_reset	140.880s	28131.555us	10	10	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1087) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault				14 test runs
	clkmgr_sec_cm	91484808980200369766444973941674038533481381648940638886630260116987490187346	213	UVM_INFO @ 10155598263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	55919047818166061932842812937756503012399251740120948485482038373407619017414	130	UVM_INFO @ 10225292033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	45939680375592655903862124092765448991904559152904749824763448228267243552810	115	UVM_INFO @ 10030560048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	97791876881122466667192804886264243183953452095108287246721328689896747550968	115	UVM_INFO @ 10020183475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	4012545961513342594425608016773259605269013700019875567253398075861471211283	152	UVM_INFO @ 10972920283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	78196731210681068966680568014724192676227617336337570515748151084879178487751	127	UVM_INFO @ 10041664269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	21256420093992918394364742163368310273239488219347745621629419218314401687291	115	UVM_INFO @ 10029694256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	106385034369768664362358626713635458933836255328362100454971519357454114810409	149	UVM_INFO @ 10077741192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	110520754452267566705428148415707726389814258197122872489098049386549861681218	211	UVM_INFO @ 10278166737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	41218417116360495838989787029594019558482968122883866037169516251122667379834	184	UVM_INFO @ 10202808970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	107942241602551292793744837161047843181889612150455751593222261264252020671213	184	UVM_INFO @ 10071522903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	35099632243550148346709783860881304981424939333042101327841011702548060164725	141	UVM_INFO @ 10086359822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	29142839382381906216274382055556632243520512500420449448709224747219878989268	204	UVM_INFO @ 10358319114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	50884888823780561582118725820061424355195258489073212497430398869655179686741	217	UVM_INFO @ 10163665001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				13 test runs
	clkmgr_shadow_reg_errors	51539257137570218856075578015925432351893754430806357639665488822030967211673	82	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	22290140291937862458429087591157023366423515088763702871734648420980277833720	81	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	12671528924668120077503995548181888187677326111943984080102891535701661336330	81	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	97796218643348943322912671666057733214595693880290923972827203399772710075531	82	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	106597044283475318099996280120655685514305765356085219473418148674963459941880	82	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	17459627584027049813355606274958329150715752933436237634692954709267135191677	82	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	78532582101645040133893676566987678184554554874328747990704211297651678990725	82	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	83150953021783495270794687634190601571304492810765060303669969283113657621358	82	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	81048189400389701778728561644778008669680784087570897393097182900974252779664	81	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	39559551506469778594825641016947712139048406558645239713901901614404979321019	81	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	106636403891534679291175474423857736353197331325600797506644253564734102908282	82	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	62114664932362079830164403286321886185166802162232639114400129186210611101562	81	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	46886078206272204085493843570388249551994814924673820080286726885251762429621	82	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_fault does not trigger!				4 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	42418566006130687404143509298422803267192896496537388872934988688981630388741	81	UVM_INFO @ 46500985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	6289266452161139719137458991727707854240500559101709250725653696548382513816	81	UVM_INFO @ 17956357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	93558950564484172110015352635674367608984455338295676992969159762339090542686	81	UVM_INFO @ 35784145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	7476826373519698538159513314388352900059631137784114693471209088346512835993	81	UVM_INFO @ 67563582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				3 test runs
	clkmgr_sec_cm	41419993829688678504656700978936031751159759545057503060113145603400891194931	86	UVM_INFO @ 6280434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	79960677555690045860816737228075969179570079023484107017762019992605964406759	149	UVM_INFO @ 70482111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	71423039761326087815079960180629636591138397614207847922814635290403630940030	96	UVM_INFO @ 13729713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.jitter_regwen (addr=*)				1 test run
	clkmgr_shadow_reg_errors_with_csr_rw	27423697222079426247803933375239873223205079508031713827629600007590525669453	81	UVM_INFO @ 2058753791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.measure_ctrl_regwen (addr=*)				1 test run
	clkmgr_shadow_reg_errors_with_csr_rw	2390623493457439051247569932456684221703902898549692494759065618372867798863	82	UVM_INFO @ 2075079842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---