Simulation Results: csrng

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.58 %
  • code
  • 96.17 %
  • assert
  • 96.94 %
  • func
  • 90.62 %
  • block
  • 98.49 %
  • line
  • 99.50 %
  • branch
  • 96.30 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.32%
V2S
99.92%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 4.000s 97.291us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 3.000s 29.783us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 3.000s 34.406us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 7.000s 85.346us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 9.000s 321.130us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 6.000s 243.726us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 3.000s 34.406us 5 5 100.00
csrng_csr_aliasing 9.000s 321.130us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 28.000s 1597.417us 200 200 100.00
alerts 500 500 100.00
csrng_alert 65.000s 3918.416us 500 500 100.00
err 499 500 99.80
csrng_err 390.000s 10000.928us 499 500 99.80
cmds 4 25 16.00
csrng_cmds 200.000s 8919.439us 4 25 16.00
life cycle 4 25 16.00
csrng_cmds 200.000s 8919.439us 4 25 16.00
stress_all 25 25 100.00
csrng_stress_all 2198.000s 118493.420us 25 25 100.00
intr_test 10 10 100.00
csrng_intr_test 3.000s 37.332us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 5.000s 143.547us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 30.000s 2073.100us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 30.000s 2073.100us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 3.000s 29.783us 1 1 100.00
csrng_csr_rw 3.000s 34.406us 5 5 100.00
csrng_csr_aliasing 9.000s 321.130us 1 1 100.00
csrng_same_csr_outstanding 6.000s 181.080us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 3.000s 29.783us 1 1 100.00
csrng_csr_rw 3.000s 34.406us 5 5 100.00
csrng_csr_aliasing 9.000s 321.130us 1 1 100.00
csrng_same_csr_outstanding 6.000s 181.080us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
csrng_sec_cm 8.000s 471.444us 5 5 100.00
csrng_tl_intg_err 16.000s 1113.611us 25 25 100.00
sec_cm_config_regwen 30 30 100.00
csrng_regwen 3.000s 75.074us 25 25 100.00
csrng_csr_rw 3.000s 34.406us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 65.000s 3918.416us 500 500 100.00
sec_cm_intersig_mubi 25 25 100.00
csrng_stress_all 2198.000s 118493.420us 25 25 100.00
sec_cm_main_sm_fsm_sparse 704 705 99.86
csrng_intr 28.000s 1597.417us 200 200 100.00
csrng_err 390.000s 10000.928us 499 500 99.80
csrng_sec_cm 8.000s 471.444us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 704 705 99.86
csrng_intr 28.000s 1597.417us 200 200 100.00
csrng_err 390.000s 10000.928us 499 500 99.80
csrng_sec_cm 8.000s 471.444us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 704 705 99.86
csrng_intr 28.000s 1597.417us 200 200 100.00
csrng_err 390.000s 10000.928us 499 500 99.80
csrng_sec_cm 8.000s 471.444us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 704 705 99.86
csrng_intr 28.000s 1597.417us 200 200 100.00
csrng_err 390.000s 10000.928us 499 500 99.80
csrng_sec_cm 8.000s 471.444us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 704 705 99.86
csrng_intr 28.000s 1597.417us 200 200 100.00
csrng_err 390.000s 10000.928us 499 500 99.80
csrng_sec_cm 8.000s 471.444us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 65.000s 3918.416us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 699 700 99.86
csrng_intr 28.000s 1597.417us 200 200 100.00
csrng_err 390.000s 10000.928us 499 500 99.80
sec_cm_constants_lc_gated 25 25 100.00
csrng_stress_all 2198.000s 118493.420us 25 25 100.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 65.000s 3918.416us 500 500 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
csrng_tl_intg_err 16.000s 1113.611us 25 25 100.00
sec_cm_aes_cipher_fsm_sparse 704 705 99.86
csrng_intr 28.000s 1597.417us 200 200 100.00
csrng_err 390.000s 10000.928us 499 500 99.80
csrng_sec_cm 8.000s 471.444us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 699 700 99.86
csrng_intr 28.000s 1597.417us 200 200 100.00
csrng_err 390.000s 10000.928us 499 500 99.80
sec_cm_aes_cipher_ctrl_sparse 699 700 99.86
csrng_intr 28.000s 1597.417us 200 200 100.00
csrng_err 390.000s 10000.928us 499 500 99.80
sec_cm_aes_cipher_fsm_local_esc 699 700 99.86
csrng_intr 28.000s 1597.417us 200 200 100.00
csrng_err 390.000s 10000.928us 499 500 99.80
sec_cm_aes_cipher_ctr_redun 704 705 99.86
csrng_intr 28.000s 1597.417us 200 200 100.00
csrng_err 390.000s 10000.928us 499 500 99.80
csrng_sec_cm 8.000s 471.444us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 699 700 99.86
csrng_intr 28.000s 1597.417us 200 200 100.00
csrng_err 390.000s 10000.928us 499 500 99.80
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:667) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 18 test runs
csrng_cmds 34224653814121977991499704675444445787870178636396881345353057139048590786714 110
UVM_INFO @ 245139312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 27670027286392304608640342062278188728012466243582251516001092960923980215140 100
UVM_INFO @ 1402687860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 89179019895215568625462326650730773552450117699647810890752491030180175846567 100
UVM_INFO @ 9877271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 75639506550593470739499836437952068486518854156613454193272315039038474410562 100
UVM_INFO @ 176558555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 97842804283436337604827006985279516822904381171942802388475164405493756640580 100
UVM_INFO @ 118850333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 70161876119903410353927238388639352915227126233671779130182377052797804717771 100
UVM_INFO @ 28002959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 81425866545880999904336745055605085541806534526396804434576805577327670783203 100
UVM_INFO @ 3741371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 54258910924120620341739854566710298971973069580094525499134964175203432319152 100
UVM_INFO @ 30078696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 53537493268446997870183683683292651905980155812480517847215135652012981999855 110
UVM_INFO @ 240867016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 56065471978440018890164341984402372271444503137483081855687251816727752399864 100
UVM_INFO @ 67083957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 78671542691493436094151932230363622501144792019651314493986746013186760520880 100
UVM_INFO @ 33086552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 11379358264996469399709419209422741075584560944209804468664207794725784526018 100
UVM_INFO @ 70825836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 98697129125523390605322012476037975570416659812592248545751826651189476831515 100
UVM_INFO @ 20375786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 27994093919438841650752316154033576801721253237355283389753784389498490114443 100
UVM_INFO @ 251954708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 36173200384176863437627415366194194639145533785863836573996174277084388386293 100
UVM_INFO @ 210124596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 78549695719946808073134276367903651994605970380252831440683281051271998324327 100
UVM_INFO @ 65932667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 34196271943971661748147423228321723235372502434647560381031464702037957180951 100
UVM_INFO @ 391473558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 23227503545665206228556471645071724254362033540341225549348678350474739582287 100
UVM_INFO @ 47836085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 7 test runs
csrng_stress_all_with_rand_reset 65837662932040729186730074371837959775842620269535252619168356200661526007020 None
csrng_stress_all_with_rand_reset 31040407831682278884496322693303389870704078845768981225291368636889159602013 None
csrng_stress_all_with_rand_reset 24620473473511651115901343530971388146914199987796172177137227184427321330614 None
csrng_stress_all_with_rand_reset 4748618509564060174603182686054608963749926362653720596015543092353992336979 None
csrng_stress_all_with_rand_reset 7192190989314824974529104141555627982625258876048202714127406665470492861061 None
csrng_stress_all_with_rand_reset 45966112606585176699353537925408703968895408884832232894102973953275031743955 None
csrng_stress_all_with_rand_reset 35329654726761715804520831508930784146385460546943934671879179436551954195430 None
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 2 test runs
csrng_stress_all_with_rand_reset 95653200009493699561033480314108047160008410031814531876335135514125415347878 169
UVM_INFO @ 297845143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 88859418683768429690963403417455199760177970433447894042037845454225262880022 104
UVM_INFO @ 990139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_env_cfg.sv:348) [cfg] Check failed csr_reseed_counter == reseed_counter[app] (* [*] vs * [*]) 1 test run
csrng_stress_all_with_rand_reset 30671218555399606116214027468928842540378605588150334923717359586563630631171 187
UVM_INFO @ 2722122107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:269) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly 1 test run
csrng_cmds 91326568581213183621550109179154866491975741573589728546238580372978959277948 108
UVM_INFO @ 133591604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:425) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits 1 test run
csrng_cmds 54097279514155989528426049986680781240487178263361133432536566680895457627459 103
UVM_INFO @ 85331525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:636) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*]) 1 test run
csrng_cmds 69557017590513046984591948868757664163963355256924059279908462623456718046441 129
UVM_INFO @ 388996610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [csrng_err_vseq] wait timeout occurred! 1 test run
csrng_err 110277877741822435629821886268044495766563770275938442554259371927411369540292 99
UVM_INFO @ 10000927727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---