Simulation Results: edn/edn0

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.61 %
  • code
  • 95.47 %
  • assert
  • 98.70 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 93.96 %
  • toggle
  • 97.12 %
  • FSM
  • 90.86 %
Validation stages
V1
100.00%
V2
98.02%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.430s 19.651us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.280s 27.569us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.220s 55.326us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 8.490s 286.732us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.920s 128.163us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 2.060s 52.800us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.220s 55.326us 5 5 100.00
edn_csr_aliasing 1.920s 128.163us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 11.110s 987.100us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 11.110s 987.100us 100 100 100.00
genbits 100 100 100.00
edn_genbits 11.110s 987.100us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.740s 22.968us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.960s 317.091us 200 200 100.00
errs 100 100 100.00
edn_err 1.850s 56.473us 100 100 100.00
disable 88 100 88.00
edn_disable 1.410s 14.380us 50 50 100.00
edn_disable_auto_req_mode 5.580s 500.000us 38 50 76.00
stress_all 30 30 100.00
edn_stress_all 10.590s 3068.278us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.350s 60.687us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.970s 45.263us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 6.040s 3298.927us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 6.040s 3298.927us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.280s 27.569us 1 1 100.00
edn_csr_rw 1.220s 55.326us 5 5 100.00
edn_csr_aliasing 1.920s 128.163us 1 1 100.00
edn_same_csr_outstanding 1.530s 34.875us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.280s 27.569us 1 1 100.00
edn_csr_rw 1.220s 55.326us 5 5 100.00
edn_csr_aliasing 1.920s 128.163us 1 1 100.00
edn_same_csr_outstanding 1.530s 34.875us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 12.460s 2495.745us 5 5 100.00
edn_tl_intg_err 4.300s 168.950us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.240s 43.258us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.960s 317.091us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 12.460s 2495.745us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 12.460s 2495.745us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 12.460s 2495.745us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 12.460s 2495.745us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.960s 317.091us 200 200 100.00
edn_sec_cm 12.460s 2495.745us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.960s 317.091us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 4.300s 168.950us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 24 30 80.00
edn_stress_all_with_rand_reset 109.560s 9359.874us 24 30 80.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 9 test runs
edn_disable_auto_req_mode 30668275786952498367008201765222618284200581118126120841258719279025672470402 94
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 42215618028476851796691435808330488508594159547499427686485354460506184408673 95
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 32887913197537912687696958686674216062981423743195837638531113137511623024102 95
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 89426584958518215609444609786625678520714895305986656753257673991471600325811 95
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 65528397507283805986211881477677327689032647209622612498748456342487562935199 94
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 13764874339769227635454283245926423301780701869898625563442126558702704830496 94
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 57888707392104166211911261684452021441163607563261668291158606101565671283926 94
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 113127675379227784064541870405045973427483159527458921913085171394508047654772 95
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 78488318506507135338937339433059341002116886006730450184142785979942225582161 95
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
edn_stress_all_with_rand_reset 53763856443289548006102138724824301988619188875475768147421635952981835156122 170
UVM_INFO @ 137861551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 38212809082212067847075960578919892312797832579321886366936639759798011997935 221
UVM_INFO @ 1405098665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 57250463819840635003605633967331129152760516740357020163216251406336821108097 183
UVM_INFO @ 1298024644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 93681666570472193482533324496693096180645623320709582891592371306377060362879 230
UVM_INFO @ 2839304442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 5877979654296331807885626061732641285990566525711135275029396622471272904462 210
UVM_INFO @ 1307851861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 77318295165460997151210141216155711172556996690339302900816793810147030027629 200
UVM_INFO @ 791395387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:425) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 2 test runs
edn_disable_auto_req_mode 104594771755984097395425047795711313079109362255504089275734958941592747490020 94
UVM_INFO @ 42408158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 59184878360077226675430209825789673938770431457393207069170051243997155443334 94
UVM_INFO @ 25168939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:576) [scoreboard] Check failed (reqs_between_reseeds_ctr < max_num_reqs_between_reseeds) Maximum number of request between reseeds in auto_req_mode * exceeded. 1 test run
edn_disable_auto_req_mode 70004000990451029018724637898904386552232250486942879763939712905466966001441 95
UVM_INFO @ 133131106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---