Simulation Results: edn/edn1

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.24 %
  • code
  • 96.15 %
  • assert
  • 97.14 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.92 %
  • toggle
  • 96.15 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
99.51%
V2S
100.00%
V3
83.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.340s 17.052us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.120s 18.996us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.140s 13.965us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.980s 146.094us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.390s 99.017us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.700s 47.993us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.140s 13.965us 5 5 100.00
edn_csr_aliasing 1.390s 99.017us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 94.760s 6261.865us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 94.760s 6261.865us 100 100 100.00
genbits 100 100 100.00
edn_genbits 94.760s 6261.865us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.400s 28.193us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.900s 236.029us 200 200 100.00
errs 100 100 100.00
edn_err 1.640s 39.407us 100 100 100.00
disable 97 100 97.00
edn_disable 1.290s 13.878us 50 50 100.00
edn_disable_auto_req_mode 4.780s 500.000us 47 50 94.00
stress_all 30 30 100.00
edn_stress_all 7.290s 364.639us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.300s 17.379us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.400s 43.193us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 4.510s 1206.418us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 4.510s 1206.418us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.120s 18.996us 1 1 100.00
edn_csr_rw 1.140s 13.965us 5 5 100.00
edn_csr_aliasing 1.390s 99.017us 1 1 100.00
edn_same_csr_outstanding 1.950s 157.584us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.120s 18.996us 1 1 100.00
edn_csr_rw 1.140s 13.965us 5 5 100.00
edn_csr_aliasing 1.390s 99.017us 1 1 100.00
edn_same_csr_outstanding 1.950s 157.584us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 6.270s 992.675us 5 5 100.00
edn_tl_intg_err 6.740s 399.234us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.340s 27.601us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.900s 236.029us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.270s 992.675us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.270s 992.675us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 6.270s 992.675us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 6.270s 992.675us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.900s 236.029us 200 200 100.00
edn_sec_cm 6.270s 992.675us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.900s 236.029us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 6.740s 399.234us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 25 30 83.33
edn_stress_all_with_rand_reset 89.800s 6232.622us 25 30 83.33

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
edn_stress_all_with_rand_reset 70655189783082058816519046242893379325016675502994817557332907129485798917406 158
UVM_INFO @ 882510091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 13064163824976986686356986684892793874687398021732167916476288115406199998315 217
UVM_INFO @ 1389712792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 72091426948257868571601028838828140695995732439214846196385681834279174988483 233
UVM_INFO @ 2550978818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 44765539109188810749949096518998897461725649520845031590954694042815913449433 259
UVM_INFO @ 861369890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 3 test runs
edn_disable_auto_req_mode 103352062589724650914751953511697480715646912714831186541505227782606847189886 95
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 22528631072889404883502507721840611571769315667729598344281180455666517607630 94
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 104788426766966797299940690717400828429872911709184457178228772861505369633914 95
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit 1 test run
edn_stress_all_with_rand_reset 47429089133156738738487431963295566148481961714060464206524786959560135978154 208
/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 644975259 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup