Simulation Results: gpio

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.25 %
  • code
  • 94.91 %
  • assert
  • 96.84 %
  • func
  • 100.00 %
  • line
  • 99.76 %
  • branch
  • 99.80 %
  • cond
  • 99.57 %
  • toggle
  • 80.52 %
Validation stages
V1
100.00%
V2
94.27%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 40 40 100.00
gpio_smoke 2.090s 93.957us 10 10 100.00
gpio_smoke_no_pullup_pulldown 1.700s 73.256us 10 10 100.00
gpio_smoke_en_cdc_prim 2.020s 109.217us 10 10 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.630s 383.179us 10 10 100.00
csr_hw_reset 1 1 100.00
gpio_csr_hw_reset 0.930s 22.202us 1 1 100.00
csr_rw 5 5 100.00
gpio_csr_rw 0.950s 30.529us 5 5 100.00
csr_bit_bash 1 1 100.00
gpio_csr_bit_bash 2.650s 396.775us 1 1 100.00
csr_aliasing 1 1 100.00
gpio_csr_aliasing 1.030s 18.023us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
gpio_csr_mem_rw_with_rand_reset 1.520s 86.578us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
gpio_csr_rw 0.950s 30.529us 5 5 100.00
gpio_csr_aliasing 1.030s 18.023us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 20 20 100.00
gpio_random_dout_din 1.580s 352.478us 10 10 100.00
gpio_random_dout_din_no_pullup_pulldown 1.800s 1225.506us 10 10 100.00
out_in_regs_read_write 10 10 100.00
gpio_dout_din_regs_random_rw 1.390s 77.030us 10 10 100.00
gpio_interrupt_programming 10 10 100.00
gpio_intr_rand_pgm 1.590s 176.787us 10 10 100.00
random_interrupt_trigger 10 10 100.00
gpio_rand_intr_trigger 3.670s 841.879us 10 10 100.00
interrupt_and_noise_filter 10 10 100.00
gpio_intr_with_filter_rand_intr_event 3.310s 92.388us 10 10 100.00
noise_filter_stress 10 10 100.00
gpio_filter_stress 28.510s 4932.976us 10 10 100.00
regs_long_reads_and_writes 10 10 100.00
gpio_random_long_reg_writes_reg_reads 5.660s 1596.869us 10 10 100.00
full_random 10 10 100.00
gpio_full_random 1.460s 197.500us 10 10 100.00
stress_all 1 10 10.00
gpio_stress_all 41.840s 21336.642us 1 10 10.00
alert_test 10 10 100.00
gpio_alert_test 0.940s 16.617us 10 10 100.00
intr_test 10 10 100.00
gpio_intr_test 0.990s 65.941us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
gpio_tl_errors 2.930s 301.332us 25 25 100.00
tl_d_illegal_access 25 25 100.00
gpio_tl_errors 2.930s 301.332us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
gpio_csr_rw 0.950s 30.529us 5 5 100.00
gpio_same_csr_outstanding 1.160s 32.067us 5 5 100.00
gpio_csr_aliasing 1.030s 18.023us 1 1 100.00
gpio_csr_hw_reset 0.930s 22.202us 1 1 100.00
tl_d_partial_access 12 12 100.00
gpio_csr_rw 0.950s 30.529us 5 5 100.00
gpio_same_csr_outstanding 1.160s 32.067us 5 5 100.00
gpio_csr_aliasing 1.030s 18.023us 1 1 100.00
gpio_csr_hw_reset 0.930s 22.202us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
gpio_tl_intg_err 1.900s 237.528us 25 25 100.00
gpio_sec_cm 1.400s 98.906us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
gpio_tl_intg_err 1.900s 237.528us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 8 10 80.00
gpio_rand_straps 0.910s 13.013us 8 10 80.00
stress_all_with_rand_reset 0 10 0.00
gpio_stress_all_with_rand_reset 10.370s 4213.478us 0 10 0.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:211) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 11 test runs
gpio_stress_all 12016521459505461159466432192118928561259025489409702131728277149103904525936 1424
UVM_INFO @ 21336642150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 106489051291815180251497406829371697289361820640147159179915290324094151754457 892
UVM_INFO @ 6413158451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 73006851415575648881598556484660550629841545623401357886696676880496687055193 81
UVM_INFO @ 4479992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 85192817030310993631993719906653316838092849404637290906973852637165447858016 522
UVM_INFO @ 3363474308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 79329822936120938444465328655091025818422738109787307866268809822712890521649 609
UVM_INFO @ 911865857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 5685663461618681308839412323003165655840195192366739345370835938218454178566 85
UVM_INFO @ 468448629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 71833435322826409384429863183827437979246505050200736279207592137350987773696 505
UVM_INFO @ 5859177633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 44055915987831907728690563000272739284066309662458407736917162559876019866182 81
UVM_INFO @ 3120391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 92291526898544531092922690072919217412917331737636097320490835187934664416475 253
UVM_INFO @ 708642899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 112380304054247396174233820350921758722142943199750164268623770498933000038644 83
UVM_INFO @ 788528064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 34072834068369170757526684358315688977711959792338504192419251780302504968506 156
UVM_INFO @ 5330365224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 5 test runs
gpio_stress_all_with_rand_reset 56138532098768838386271477330324066515080929716625906512150598038457588628677 85
UVM_INFO @ 214616328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 46464834399957763563557442124421431815915813767163491993153627283510657889956 85
UVM_INFO @ 790555364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 789122360901268477260256234645273381143944600932469622125444843754253235516 84
UVM_INFO @ 1313637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 31922390945291242333084523456359617177152261109223949546744658482387597611203 85
UVM_INFO @ 1263928613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 8703282478429760336356853273468909859573993278899450496040903565897083827445 308
UVM_INFO @ 531864098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [gpio_common_vseq] Check failed (vseq_done) 5 test runs
gpio_stress_all_with_rand_reset 83109705537967258845289646555514920728082747006266904693050208238156533424811 86
UVM_INFO @ 71842163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 8268078646675754412044380743493368790255771837327939525474061645357613958600 166
UVM_INFO @ 2331050854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 91206442431763750496097492885438801248266866377812546009977867870210785050536 246
UVM_INFO @ 4213478171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 11378966546685302878762689153643182526385162099649675130370004119281005536351 86
UVM_INFO @ 50595037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 111164677397582073694697586826360590270612120870670595974422193414717368603662 86
UVM_INFO @ 207309991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---