Simulation Results: hmac

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.14 %
  • code
  • 88.30 %
  • assert
  • 97.60 %
  • func
  • 99.52 %
  • line
  • 99.64 %
  • branch
  • 99.35 %
  • cond
  • 96.36 %
  • toggle
  • 46.17 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 15.430s 491.023us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.110s 20.656us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.170s 29.816us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 14.400s 1897.319us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.210s 6525.502us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 592.350s 135316.826us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.170s 29.816us 5 5 100.00
hmac_csr_aliasing 5.210s 6525.502us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 116.030s 43589.026us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 126.230s 16585.280us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 287.720s 10239.081us 30 30 100.00
hmac_test_sha384_vectors 603.250s 42730.871us 75 75 100.00
hmac_test_sha512_vectors 621.260s 97730.102us 75 75 100.00
hmac_test_hmac256_vectors 15.480s 526.798us 50 50 100.00
hmac_test_hmac384_vectors 18.100s 1247.805us 60 60 100.00
hmac_test_hmac512_vectors 20.260s 584.706us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 44.180s 21497.701us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 2178.310s 20824.475us 10 10 100.00
error 10 10 100.00
hmac_error 117.500s 12067.478us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 118.930s 3646.361us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 15.430s 491.023us 10 10 100.00
hmac_long_msg 116.030s 43589.026us 10 10 100.00
hmac_back_pressure 126.230s 16585.280us 25 25 100.00
hmac_datapath_stress 2178.310s 20824.475us 10 10 100.00
hmac_burst_wr 44.180s 21497.701us 50 50 100.00
hmac_stress_all 5619.250s 211922.602us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 15.430s 491.023us 10 10 100.00
hmac_long_msg 116.030s 43589.026us 10 10 100.00
hmac_back_pressure 126.230s 16585.280us 25 25 100.00
hmac_datapath_stress 2178.310s 20824.475us 10 10 100.00
hmac_wipe_secret 118.930s 3646.361us 10 10 100.00
hmac_test_sha256_vectors 287.720s 10239.081us 30 30 100.00
hmac_test_sha384_vectors 603.250s 42730.871us 75 75 100.00
hmac_test_sha512_vectors 621.260s 97730.102us 75 75 100.00
hmac_test_hmac256_vectors 15.480s 526.798us 50 50 100.00
hmac_test_hmac384_vectors 18.100s 1247.805us 60 60 100.00
hmac_test_hmac512_vectors 20.260s 584.706us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 15.430s 491.023us 10 10 100.00
hmac_long_msg 116.030s 43589.026us 10 10 100.00
hmac_back_pressure 126.230s 16585.280us 25 25 100.00
hmac_datapath_stress 2178.310s 20824.475us 10 10 100.00
hmac_burst_wr 44.180s 21497.701us 50 50 100.00
hmac_error 117.500s 12067.478us 10 10 100.00
hmac_wipe_secret 118.930s 3646.361us 10 10 100.00
hmac_test_sha256_vectors 287.720s 10239.081us 30 30 100.00
hmac_test_sha384_vectors 603.250s 42730.871us 75 75 100.00
hmac_test_sha512_vectors 621.260s 97730.102us 75 75 100.00
hmac_test_hmac256_vectors 15.480s 526.798us 50 50 100.00
hmac_test_hmac384_vectors 18.100s 1247.805us 60 60 100.00
hmac_test_hmac512_vectors 20.260s 584.706us 75 75 100.00
hmac_stress_all 5619.250s 211922.602us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 5619.250s 211922.602us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.930s 15.761us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.940s 25.882us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 3.430s 1833.014us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 3.430s 1833.014us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.110s 20.656us 1 1 100.00
hmac_csr_rw 1.170s 29.816us 5 5 100.00
hmac_csr_aliasing 5.210s 6525.502us 1 1 100.00
hmac_same_csr_outstanding 2.500s 218.499us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.110s 20.656us 1 1 100.00
hmac_csr_rw 1.170s 29.816us 5 5 100.00
hmac_csr_aliasing 5.210s 6525.502us 1 1 100.00
hmac_same_csr_outstanding 2.500s 218.499us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.310s 449.383us 5 5 100.00
hmac_tl_intg_err 5.120s 286.981us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 5.120s 286.981us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 15.430s 491.023us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.970s 127.705us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 966.920s 252396.486us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.350s 159.172us 1 1 100.00