Simulation Results: lc_ctrl/volatile_unlock_disabled

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.25 %
  • code
  • 85.87 %
  • assert
  • 94.83 %
  • func
  • 96.06 %
  • line
  • 97.28 %
  • branch
  • 94.05 %
  • cond
  • 81.49 %
  • toggle
  • 88.33 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 5.270s 461.441us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.190s 54.353us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.180s 38.191us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.500s 1227.048us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.740s 642.988us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.670s 198.279us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.180s 38.191us 5 5 100.00
lc_ctrl_csr_aliasing 1.740s 642.988us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 8.710s 85.166us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 10.360s 1656.868us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.220s 27.860us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 2.820s 331.485us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 12.070s 393.781us 20 20 100.00
lc_errors 18 20 90.00
lc_ctrl_errors 12.640s 530.504us 18 20 90.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 12.070s 393.781us 20 20 100.00
lc_ctrl_prog_failure 2.820s 331.485us 20 20 100.00
lc_ctrl_errors 12.640s 530.504us 18 20 90.00
lc_ctrl_security_escalation 9.870s 417.500us 20 20 100.00
lc_ctrl_jtag_state_failure 42.950s 8733.453us 20 20 100.00
lc_ctrl_jtag_prog_failure 13.540s 1359.186us 20 20 100.00
lc_ctrl_jtag_errors 55.610s 4018.125us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 7.060s 427.767us 20 20 100.00
lc_ctrl_jtag_state_post_trans 21.260s 2138.738us 20 20 100.00
lc_ctrl_jtag_prog_failure 13.540s 1359.186us 20 20 100.00
lc_ctrl_jtag_errors 55.610s 4018.125us 20 20 100.00
lc_ctrl_jtag_access 13.540s 26326.572us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 21.380s 1169.918us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.150s 465.648us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.140s 194.458us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 18.870s 1852.934us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 7.610s 697.253us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.930s 51.207us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.860s 5150.914us 10 10 100.00
lc_ctrl_jtag_alert_test 1.960s 138.611us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 17.320s 6538.018us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.370s 22.662us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 209.520s 47369.403us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.520s 37.835us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.280s 147.693us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.280s 147.693us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.190s 54.353us 1 1 100.00
lc_ctrl_csr_rw 1.180s 38.191us 5 5 100.00
lc_ctrl_csr_aliasing 1.740s 642.988us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.870s 53.584us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.190s 54.353us 1 1 100.00
lc_ctrl_csr_rw 1.180s 38.191us 5 5 100.00
lc_ctrl_csr_aliasing 1.740s 642.988us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.870s 53.584us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 9.920s 510.382us 5 5 100.00
lc_ctrl_tl_intg_err 3.230s 241.591us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.230s 241.591us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 10.360s 1656.868us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 12.070s 393.781us 20 20 100.00
lc_ctrl_sec_cm 9.920s 510.382us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 12.070s 393.781us 20 20 100.00
lc_ctrl_sec_cm 9.920s 510.382us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.070s 393.781us 20 20 100.00
lc_ctrl_sec_cm 9.920s 510.382us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.070s 393.781us 20 20 100.00
lc_ctrl_sec_cm 9.920s 510.382us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 12.070s 393.781us 20 20 100.00
lc_ctrl_sec_cm 9.920s 510.382us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.070s 393.781us 20 20 100.00
lc_ctrl_sec_cm 9.920s 510.382us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.070s 393.781us 20 20 100.00
lc_ctrl_sec_cm 9.920s 510.382us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 12.070s 393.781us 20 20 100.00
lc_ctrl_sec_cm 9.920s 510.382us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 9.870s 417.500us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 8.710s 85.166us 20 20 100.00
lc_ctrl_jtag_state_post_trans 21.260s 2138.738us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.810s 2471.095us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 9.810s 2471.095us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 10.900s 899.925us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.020s 855.772us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.020s 855.772us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 105.540s 24155.646us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
lc_ctrl_stress_all_with_rand_reset 114114406314736410059561164795285507843049818470729701172855877309838585079711 212
UVM_INFO @ 230320531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 50949774813273468388678435035439468896815780286797601495104856636806297771651 941
UVM_INFO @ 6846885074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 70813473086852594297593392226429932813553377440053694998728985395423394973642 1745
UVM_INFO @ 10370949635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 105783788375516430565573422070048620195165311391016657351825654621888458278800 4054
UVM_INFO @ 1253862723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 92926505010058888372515718691834714769149693136773646629500931422755215002671 5424
UVM_INFO @ 68679246516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 64119130684156744965604102111438370227499647844786169377958203477768077686369 2702
UVM_INFO @ 841116027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_errors 100947888320388050028620175663848406327336672575589429763966862217434030568116 381
UVM_INFO @ 120927018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 30930697786152680218408250898527163996317946424581486537118968183552399129631 1617
UVM_INFO @ 347571590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---