Simulation Results: lc_ctrl/volatile_unlock_enabled

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.43 %
  • code
  • 85.91 %
  • assert
  • 94.97 %
  • func
  • 96.42 %
  • line
  • 97.26 %
  • branch
  • 94.00 %
  • cond
  • 81.76 %
  • toggle
  • 88.33 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 4.830s 168.418us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.130s 17.785us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.210s 49.646us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.790s 75.309us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.190s 18.094us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.700s 26.679us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.210s 49.646us 5 5 100.00
lc_ctrl_csr_aliasing 1.190s 18.094us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 8.730s 445.227us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 11.800s 1270.529us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.200s 13.838us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 3.180s 551.662us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 12.820s 1252.323us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 9.280s 491.320us 19 20 95.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 12.820s 1252.323us 20 20 100.00
lc_ctrl_prog_failure 3.180s 551.662us 20 20 100.00
lc_ctrl_errors 9.280s 491.320us 19 20 95.00
lc_ctrl_security_escalation 9.120s 1812.962us 20 20 100.00
lc_ctrl_jtag_state_failure 54.340s 8030.166us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.820s 845.498us 20 20 100.00
lc_ctrl_jtag_errors 60.240s 9812.956us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 8.030s 541.078us 20 20 100.00
lc_ctrl_jtag_state_post_trans 21.510s 1228.085us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.820s 845.498us 20 20 100.00
lc_ctrl_jtag_errors 60.240s 9812.956us 19 20 95.00
lc_ctrl_jtag_access 15.900s 1465.025us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 17.480s 6238.056us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 2.880s 141.991us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.480s 786.130us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 12.440s 4123.977us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 12.300s 6231.040us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.780s 48.055us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.400s 702.730us 10 10 100.00
lc_ctrl_jtag_alert_test 1.980s 186.927us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 11.440s 3585.306us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.620s 23.853us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 235.920s 11487.808us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.340s 28.034us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.200s 286.434us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.200s 286.434us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.130s 17.785us 1 1 100.00
lc_ctrl_csr_rw 1.210s 49.646us 5 5 100.00
lc_ctrl_csr_aliasing 1.190s 18.094us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.420s 233.193us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.130s 17.785us 1 1 100.00
lc_ctrl_csr_rw 1.210s 49.646us 5 5 100.00
lc_ctrl_csr_aliasing 1.190s 18.094us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.420s 233.193us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 10.050s 921.816us 5 5 100.00
lc_ctrl_tl_intg_err 3.900s 535.816us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.900s 535.816us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 11.800s 1270.529us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 12.820s 1252.323us 20 20 100.00
lc_ctrl_sec_cm 10.050s 921.816us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 12.820s 1252.323us 20 20 100.00
lc_ctrl_sec_cm 10.050s 921.816us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.820s 1252.323us 20 20 100.00
lc_ctrl_sec_cm 10.050s 921.816us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.820s 1252.323us 20 20 100.00
lc_ctrl_sec_cm 10.050s 921.816us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 12.820s 1252.323us 20 20 100.00
lc_ctrl_sec_cm 10.050s 921.816us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.820s 1252.323us 20 20 100.00
lc_ctrl_sec_cm 10.050s 921.816us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.820s 1252.323us 20 20 100.00
lc_ctrl_sec_cm 10.050s 921.816us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 12.820s 1252.323us 20 20 100.00
lc_ctrl_sec_cm 10.050s 921.816us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 9.120s 1812.962us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 8.730s 445.227us 20 20 100.00
lc_ctrl_jtag_state_post_trans 21.510s 1228.085us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 10.080s 3577.047us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 10.080s 3577.047us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 8.490s 1764.993us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 7.090s 1808.192us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 7.090s 1808.192us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 61.160s 12443.731us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1296) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 33409006092984081795530717148857409124575142318408778060144998792596108325739 1466
UVM_INFO @ 1202501812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 71944078502587325796659427932864042430908990907752289110402134802073605781259 4278
UVM_INFO @ 1599030168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 37308073733747184593438558319379317378385509724049513514354136533642273391858 8458
UVM_INFO @ 3179183106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 63139614374284313426076002969662940575550845074014979663192588872410921780933 2358
UVM_INFO @ 1953789927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 3 test runs
lc_ctrl_stress_all_with_rand_reset 48030087040806415172688959246102082890996042411665296194865050898894473583892 1335
UVM_INFO @ 567731394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 30086261252600526042070955649072402549347068343788274033825826934494046148205 1629
UVM_INFO @ 11279199095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 85379893890484913182002222817162864511839669873260689793216198718358963528308 3111
UVM_INFO @ 913693493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:933) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 18314371590699372976240529015267840202844028658173826137523567211612389787671 5606
UVM_INFO @ 3537859722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---