Simulation Results: otbn

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.81 %
  • code
  • 87.07 %
  • assert
  • 97.35 %
  • func
  • 100.00 %
  • block
  • 99.33 %
  • line
  • 99.54 %
  • branch
  • 95.19 %
  • toggle
  • 85.93 %
  • FSM
  • 67.61 %
Validation stages
V1
100.00%
V2
97.55%
V2S
97.87%
V3
20.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 17.000s 100.060us 1 1 100.00
otbn_smoke_vectorized 10.000s 63.126us 1 1 100.00
single_binary 100 100 100.00
otbn_single 701.000s 2070.714us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 155.027us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 6.000s 16.761us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 10.000s 149.328us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 41.111us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 10.000s 134.488us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 6.000s 16.761us 5 5 100.00
otbn_csr_aliasing 4.000s 41.111us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 47.000s 775.762us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 36.000s 3579.383us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 9 10 90.00
otbn_reset 71.000s 455.363us 9 10 90.00
multi_error 1 1 100.00
otbn_multi_err 89.000s 240.538us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 184.000s 459.333us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 144.000s 378.718us 10 10 100.00
lc_escalation 58 60 96.67
otbn_escalate 25.000s 217.150us 58 60 96.67
zero_state_err_urnd 4 5 80.00
otbn_zero_state_err_urnd 11.000s 165.068us 4 5 80.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 30.000s 447.613us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 12.000s 53.911us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 7.000s 20.688us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 15.000s 567.113us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 15.000s 567.113us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 5.000s 155.027us 1 1 100.00
otbn_csr_rw 6.000s 16.761us 5 5 100.00
otbn_csr_aliasing 4.000s 41.111us 1 1 100.00
otbn_same_csr_outstanding 10.000s 30.681us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 5.000s 155.027us 1 1 100.00
otbn_csr_rw 6.000s 16.761us 5 5 100.00
otbn_csr_aliasing 4.000s 41.111us 1 1 100.00
otbn_same_csr_outstanding 10.000s 30.681us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 45.000s 102.206us 10 10 100.00
otbn_dmem_err 19.000s 42.073us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 16.000s 620.207us 5 5 100.00
otbn_controller_ispr_rdata_err 34.000s 73.630us 5 5 100.00
otbn_mac_bignum_acc_err 15.000s 121.538us 5 5 100.00
otbn_urnd_err 7.000s 11.880us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 15.000s 92.305us 5 5 100.00
otbn_mem_gnt_acc_err 1 2 50.00
otbn_mem_gnt_acc_err 197.000s 10003.431us 1 2 50.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 10.000s 18.237us 9 10 90.00
tl_intg_err 30 30 100.00
otbn_sec_cm 966.000s 3416.173us 5 5 100.00
otbn_tl_intg_err 31.000s 144.191us 25 25 100.00
passthru_mem_tl_intg_err 4 5 80.00
otbn_passthru_mem_tl_intg_err 81.000s 240.867us 4 5 80.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 966.000s 3416.173us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 966.000s 3416.173us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 17.000s 100.060us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 19.000s 42.073us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 45.000s 102.206us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 31.000s 144.191us 25 25 100.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 25.000s 217.150us 58 60 96.67
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 45.000s 102.206us 10 10 100.00
otbn_dmem_err 19.000s 42.073us 15 15 100.00
otbn_zero_state_err_urnd 11.000s 165.068us 4 5 80.00
otbn_illegal_mem_acc 15.000s 92.305us 5 5 100.00
otbn_sec_cm 966.000s 3416.173us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 966.000s 3416.173us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 701.000s 2070.714us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 45.000s 102.206us 10 10 100.00
otbn_dmem_err 19.000s 42.073us 15 15 100.00
otbn_zero_state_err_urnd 11.000s 165.068us 4 5 80.00
otbn_illegal_mem_acc 15.000s 92.305us 5 5 100.00
otbn_sec_cm 966.000s 3416.173us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 966.000s 3416.173us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 25.000s 217.150us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 45.000s 102.206us 10 10 100.00
otbn_dmem_err 19.000s 42.073us 15 15 100.00
otbn_zero_state_err_urnd 11.000s 165.068us 4 5 80.00
otbn_illegal_mem_acc 15.000s 92.305us 5 5 100.00
otbn_sec_cm 966.000s 3416.173us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 966.000s 3416.173us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 701.000s 2070.714us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 24.000s 62.073us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 11.000s 22.757us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 98.000s 287.900us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 98.000s 287.900us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 19.000s 498.063us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 966.000s 3416.173us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 966.000s 3416.173us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 9 10 90.00
otbn_rf_bignum_intg_err 18.000s 128.976us 9 10 90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 966.000s 3416.173us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 966.000s 3416.173us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 27.000s 50.718us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 27.000s 50.718us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 11.000s 19.762us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 701.000s 2070.714us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 701.000s 2070.714us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 701.000s 2070.714us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 184.000s 459.333us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 701.000s 2070.714us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 701.000s 2070.714us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 40.000s 86.490us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 701.000s 2070.714us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 966.000s 3416.173us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
otbn_stress_all_with_rand_reset 380.000s 5171.657us 2 10 20.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1297) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
otbn_stress_all_with_rand_reset 115520818429540523535121179525144980503065675647054304727986939816632663265757 214
UVM_INFO @ 1102079452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 113518825531853682428115434721659714912509976616640693717717502909154461513094 278
UVM_INFO @ 3352825640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 14674315409142264458095604195138410646544996620371176314796856319806669159025 155
UVM_INFO @ 111919828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 77664886050548050686874341939547537679080025337503354694405925196063091549828 184
UVM_INFO @ 259944897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 103930128246788394499446140345549082112313757669315483838917135429801969381700 300
UVM_INFO @ 662230937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 38847296834982391446981180897232611650480895208364794364519346370251213416878 158
UVM_INFO @ 610680280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:322) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 2 test runs
otbn_escalate 7279853250813379181712296309544875453658199778589540012086267301288915534209 105
UVM_INFO @ 4147045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 7781217574207364467474391091593516223235296534167235391634438735071469893687 108
UVM_INFO @ 5666552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:349) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 43689678536748052019207282808571853414138127646347534228589368108934483479385 484
UVM_INFO @ 4772305734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,304): Assertion MatchingReqURND_A has failed 1 test run
otbn_zero_state_err_urnd 1512843574802718039006608920924912809904498412551146255599394361527385371880 103
UVM_ERROR @ 7592089 ps: (tb.sv:304) [ASSERT FAILED] MatchingReqURND_A
UVM_INFO @ 7592089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_mem_gnt_acc_err_vseq.sv:41) [otbn_mem_gnt_acc_err_vseq] timeout occurred! 1 test run
otbn_mem_gnt_acc_err 107826430073251485896302137906810348082042385582890245602718729177537063462897 110
UVM_INFO @ 10003430938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 15059259384475483354893500645981888235513235549048465703466535072294047652598 91
UVM_INFO @ 96046381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_rf_bignum_intg_err 57183659173323003517364763111083385584520774907518175197103508274786929547974 109
UVM_INFO @ 174515000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:349) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 29576820150159031967171181545431248233475408875185241188896780060956964979998 224
UVM_INFO @ 1128351677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,299): Assertion MatchingReqRND_A has failed 1 test run
otbn_reset 14634886169606386109934600279122354463762454721072885902649874193289517711966 160
UVM_ERROR @ 108235185 ps: (tb.sv:299) [ASSERT FAILED] MatchingReqRND_A
UVM_INFO @ 108235185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,296): Assertion MatchingStatus_A has failed 1 test run
otbn_partial_wipe 96932357378777463176888428981171187997917957454648902958301361040504032081188 108
UVM_ERROR @ 3910488 ps: (tb.sv:296) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 3910488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---