Simulation Results: otp_ctrl

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.99 %
  • code
  • 85.24 %
  • assert
  • 95.53 %
  • func
  • 92.19 %
  • line
  • 90.14 %
  • branch
  • 86.65 %
  • cond
  • 93.95 %
  • toggle
  • 92.61 %
  • FSM
  • 62.85 %
Validation stages
V1
96.15%
V2
94.82%
V2S
95.45%
V3
24.75%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.940s 114.494us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 12.590s 953.808us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.380s 213.566us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 2.150s 631.807us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.270s 1163.749us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.840s 467.429us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.970s 288.618us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 2.150s 631.807us 5 5 100.00
otp_ctrl_csr_aliasing 4.840s 467.429us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.810s 63.295us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.950s 142.538us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 21.140s 906.351us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 11.810s 3232.380us 300 300 100.00
partition_check 38 60 63.33
otp_ctrl_background_chks 39.260s 2738.958us 10 10 100.00
otp_ctrl_check_fail 51.360s 24521.175us 28 50 56.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 16.130s 5498.514us 30 30 100.00
partition_lock 30 30 100.00
otp_ctrl_dai_lock 102.240s 14477.815us 30 30 100.00
interface_key_check 7 10 70.00
otp_ctrl_parallel_key_req 22.320s 714.064us 7 10 70.00
lc_interactions 209 210 99.52
otp_ctrl_parallel_lc_req 22.850s 12195.402us 10 10 100.00
otp_ctrl_parallel_lc_esc 50.080s 18225.130us 199 200 99.50
otp_dai_errors 22 25 88.00
otp_ctrl_dai_errs 71.430s 31107.089us 22 25 88.00
otp_macro_errors 3 10 30.00
otp_ctrl_macro_errs 33.610s 17993.190us 3 10 30.00
test_access 10 10 100.00
otp_ctrl_test_access 85.810s 32493.911us 10 10 100.00
stress_all 7 10 70.00
otp_ctrl_stress_all 530.300s 191461.516us 7 10 70.00
intr_test 10 10 100.00
otp_ctrl_intr_test 2.070s 147.543us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 3.790s 824.411us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 10.090s 2723.548us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 10.090s 2723.548us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 3.380s 213.566us 1 1 100.00
otp_ctrl_csr_rw 2.150s 631.807us 5 5 100.00
otp_ctrl_csr_aliasing 4.840s 467.429us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.140s 263.421us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 3.380s 213.566us 1 1 100.00
otp_ctrl_csr_rw 2.150s 631.807us 5 5 100.00
otp_ctrl_csr_aliasing 4.840s 467.429us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.140s 263.421us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
tl_intg_err 30 30 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
otp_ctrl_tl_intg_err 49.350s 19172.722us 25 25 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
otp_ctrl_tl_intg_err 49.350s 19172.722us 25 25 100.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 12.590s 953.808us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 12.590s 953.808us 10 10 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_dai_fsm_local_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 50.080s 18225.130us 199 200 99.50
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_lci_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 50.080s 18225.130us 199 200 99.50
sec_cm_kdi_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 50.080s 18225.130us 199 200 99.50
sec_cm_part_fsm_local_esc 202 210 96.19
otp_ctrl_parallel_lc_esc 50.080s 18225.130us 199 200 99.50
otp_ctrl_macro_errs 33.610s 17993.190us 3 10 30.00
sec_cm_scrmbl_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 50.080s 18225.130us 199 200 99.50
sec_cm_timer_fsm_local_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 50.080s 18225.130us 199 200 99.50
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_dai_fsm_global_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 50.080s 18225.130us 199 200 99.50
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_lci_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 50.080s 18225.130us 199 200 99.50
sec_cm_kdi_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 50.080s 18225.130us 199 200 99.50
sec_cm_part_fsm_global_esc 202 210 96.19
otp_ctrl_parallel_lc_esc 50.080s 18225.130us 199 200 99.50
otp_ctrl_macro_errs 33.610s 17993.190us 3 10 30.00
sec_cm_scrmbl_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 50.080s 18225.130us 199 200 99.50
sec_cm_timer_fsm_global_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 50.080s 18225.130us 199 200 99.50
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 11.810s 3232.380us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 28 50 56.00
otp_ctrl_check_fail 51.360s 24521.175us 28 50 56.00
sec_cm_part_mem_regren 30 30 100.00
otp_ctrl_dai_lock 102.240s 14477.815us 30 30 100.00
sec_cm_part_mem_sw_unreadable 30 30 100.00
otp_ctrl_dai_lock 102.240s 14477.815us 30 30 100.00
sec_cm_part_mem_sw_unwritable 30 30 100.00
otp_ctrl_dai_lock 102.240s 14477.815us 30 30 100.00
sec_cm_lc_part_mem_sw_noaccess 30 30 100.00
otp_ctrl_dai_lock 102.240s 14477.815us 30 30 100.00
sec_cm_access_ctrl_mubi 30 30 100.00
otp_ctrl_dai_lock 102.240s 14477.815us 30 30 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 12.590s 953.808us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 30 30 100.00
otp_ctrl_dai_lock 102.240s 14477.815us 30 30 100.00
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 12.590s 953.808us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 175.370s 19291.135us 5 5 100.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 16.130s 5498.514us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 12.590s 953.808us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 12.590s 953.808us 10 10 100.00
sec_cm_macro_mem_integrity 3 10 30.00
otp_ctrl_macro_errs 33.610s 17993.190us 3 10 30.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 18.690s 9192.515us 1 1 100.00
stress_all_with_rand_reset 24 100 24.00
otp_ctrl_stress_all_with_rand_reset 156.130s 27568.807us 24 100 24.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 44 test runs
otp_ctrl_check_fail 740012348074330772984379442251006394471471197679819850121944474436572136697 4633
UVM_INFO @ 790870574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 65178613804978835569746264710964193495601569765810472600641504473598820794927 6511
UVM_INFO @ 350863152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 66192823017443810545997054396599736010383948033117443134972611890979514839444 8035
UVM_INFO @ 11406820527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 52407578141861582932661904316213679807407382008198549542617568970685543863025 117
UVM_INFO @ 60139302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 104949528053511018937159627171543901557575169853232676092822900613321442204375 393
UVM_INFO @ 86287845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42382008314144998160505862985987396738608901044989506640388322267054754393208 526
UVM_INFO @ 323243605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 56274061399019150132857322561411886008507448495603726499502857573519774971052 1507
UVM_INFO @ 443289976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 22028870802378873579491862058356647381451217362710670359190081942493215149710 20442
UVM_INFO @ 1567298061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 6386459427907429903010358593989594552344298987870439068570783310412379772732 397
UVM_INFO @ 51228224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 104503309460708042050742261671816612066576031626284713518441486657745064380204 6770
UVM_INFO @ 9721423383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 41417984352176093501187283367028402997418633174795978247148889919521246781945 7531
UVM_INFO @ 17993190296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 52620519059125633450479432820843767955054924874165137503224804292552382320132 1821
UVM_INFO @ 60007817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 41972434114105247786526913201867185390526856410302813805416819571184311917311 4298
UVM_INFO @ 740962312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 48334780383848755225011885932400567484301705114965294359048468684813802207098 149
UVM_INFO @ 38652906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 86098737275570996684933494647183460246269398702553957525021684092536224959217 4839
UVM_INFO @ 3503361843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 84419611666565227809331693235811663914973548127073860151180999413505567901643 6823
UVM_INFO @ 2965716073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 84834483914330103223512190305425938552103427067374127446181128611068491277032 1116
UVM_INFO @ 558090575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 38117880697623192443692525536239988775687953444954138831696903078453568663498 3546
UVM_INFO @ 684016685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 7424980609007047454863842393485436633084791001539586739186462458799984737039 7139
UVM_INFO @ 6049073083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 63502985675165349532348816836593926659161999708456601188117116823888062015613 18915
UVM_INFO @ 1582979940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 31782909816268168111778900079447607340152558253304864339988365967926412813685 3193
UVM_INFO @ 6177040008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 67288186060693757414448908997441140961796699320322558290709042559435386389924 1271
UVM_INFO @ 69990501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 88709646479953928031869353241477137556065601051374944856231778534307141097671 155
UVM_INFO @ 54762307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 27000185467349891246824944552023954837170037658404041564531917771468810109621 2473
UVM_INFO @ 193885793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 108749917058060417475079709858937495583487084782275184164881169016381002701451 4526
UVM_INFO @ 137481233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 8737030833492012675319520293067127743247251954842008410806728077574082916526 473
UVM_INFO @ 107761782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 61155641237236801824560847441410682567565058811671212878335064662019502154078 233
UVM_INFO @ 42361324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2317385016626291700132182963017183480019242094497808661536911582271358696169 15352
UVM_INFO @ 6480405310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 57478535848901237593305616088257890086404990232458229125936089012428413739928 16680
UVM_INFO @ 24521175014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 17724567945083214673327487233363211653334067020951643659312726613343696264547 11501
UVM_INFO @ 15875420481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53936119444340498766866979472288178075895280140376317537511984387397816601293 1426
UVM_INFO @ 603346436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 27448792491122320414151222109706358534638614521167235625405367351017831238781 3254
UVM_INFO @ 639848236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 84574760055089852382556150135157786165256820057413169189008722639036292748306 8711
UVM_INFO @ 838544292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 72394139676713877378878380169366059715304508243196292469518090375980483533215 175
UVM_INFO @ 1022888437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 45419871544460026290026851955347976837049653028278635539838118589798803371606 6245
UVM_INFO @ 8524258465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 21678953378875254806403955990039109058723044539552632801691859186885333190337 3244
UVM_INFO @ 817196516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 15994397084389524907817481664583643663155042070420322175202471824641627284515 1065
UVM_INFO @ 3545927841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 53213618449395535144350588109309639956071419729637799617830717344735545777752 6285
UVM_INFO @ 5782523272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 68894835035736231467094184037508181819855293459655467312147704455051819409970 21191
UVM_INFO @ 1445654466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 34776316573064612755884042184270175594969573225243898951807180647137187177669 465
UVM_INFO @ 684324634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 71225223827763730058901737345064158194648422238903174505891659528387279919895 11445
UVM_INFO @ 55525505261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 75885792180920896327294826810394218035365791389035337658174759350186725381863 8513
UVM_INFO @ 1369329991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103188995794565381156360215017224376506531104719570064618557318700560068677525 958
UVM_INFO @ 448923647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23955883962029340526437504855247236422782481310508169255847789940451935164241 159
UVM_INFO @ 99228977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1205) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 28 test runs
otp_ctrl_stress_all_with_rand_reset 53433254966948759870703269813273611350481870131422626617956896143330778536795 14371
UVM_INFO @ 46780697232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 68830470429832661872634787894203067450374097223753703182579311253562023973290 2678
UVM_INFO @ 16190981529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29749175791654343842484760077127406324643539988290537992772992145060515213640 7166
UVM_INFO @ 7591644872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91408627525319835144767734257870737660446420291628522782009233552318435359985 5893
UVM_INFO @ 2596847397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12884777566051346696238290148702074037231216540583282811247626660593320167274 821
UVM_INFO @ 101345818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 74354388900852545975270470666166621616554978218634817818407133593360558029946 2639
UVM_INFO @ 4118532633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33117338799052665799458858581383301757530147868382506776319137567033516935488 4743
UVM_INFO @ 1307292400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18581479820741567932642101517448455104706889996167415609823988536029193566754 2469
UVM_INFO @ 3190396966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86383118221986973124390421458289627701912370413743914721196167102468126435230 153
UVM_INFO @ 637426276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29712626923313101182671812649179741540485311267837431262213852126414662696855 4528
UVM_INFO @ 987534131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61643632879969112385300833634788961822506850766647154937540988809104197928778 3661
UVM_INFO @ 8026595035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 113235613663210407885624086005264814520390344724624171598741739047634071781742 790
UVM_INFO @ 7476697788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 92741427266590299258521615012786591084776160951920659878172277656095162055628 2025
UVM_INFO @ 340490480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85611906674315273794028705643492402396529400900314469573952155559075692718126 4580
UVM_INFO @ 2690270291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 102868827661533102166492441461838095186778708246837745219461099547967929279002 15965
UVM_INFO @ 872488807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 36482470638666451857009184863338354969131688503697680597128976096479575830378 7151
UVM_INFO @ 48131588034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86653481276391759073675487806321876537400351470083925119708443969887822451195 355
UVM_INFO @ 219129593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 59951025525042378584949870897882777389363216927813741590385621167622526334306 4249
UVM_INFO @ 687780644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 65416618539297044006509325623628024853808403187986947601049604978446714307411 216
UVM_INFO @ 974559856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12095543473239355434567243541580096635236754720397153481173054933794515040709 2894
UVM_INFO @ 8401456773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 49278794428422866654545379642286479629686370373025756946515292869311334054575 1639
UVM_INFO @ 1495050317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 52245347289772461222672844388364042566361192504458517876799800854960076036391 171
UVM_INFO @ 35094866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 15558200381305982121991426933030982235768253021083632587437804737745462766335 6755
UVM_INFO @ 1042757002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 101040568381696970099928874813459878306953311227542307709473082151297726993593 155
UVM_INFO @ 94629181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50636685209456693412789982289340997940661814631400673541997029362634910328696 13311
UVM_INFO @ 49969828309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 148210517583038475346016027276998290877334472952780597646589767557966373104 10125
UVM_INFO @ 1963285826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1402546364795207889570574198958523592868531072042817499598819861221085504805 7931
UVM_INFO @ 17519576392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 46276891293249544679842892259592507701266580459468701606128981915075632954642 9638
UVM_INFO @ 1523214712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1824) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 20 test runs
otp_ctrl_stress_all_with_rand_reset 5216168429340778351933067893414760920226079362552350200854310717898966847343 3251
UVM_INFO @ 563355058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23616200863685747923801461950176150638307227409508895554187085872190499096214 15535
UVM_INFO @ 1965584380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95812044727259851823898603392171824596276969758456600797426988100685491268869 99
UVM_INFO @ 53580502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 67344842386590706469672503387499343146241692421080734658501924652344059061761 414
UVM_INFO @ 209772720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44991983234615388251149473575875850008795660584021522419515183091969292095466 4571
UVM_INFO @ 1662846685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42253417147056315791295771429900751124383013771911678104607215866126078497659 453
UVM_INFO @ 332368203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 92679561884525403439419764073611711792366130934951889381645298466575556151764 19131
UVM_INFO @ 8170043517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 30202924906023393329202427083165628202127284072294445702143143105843437702318 22275
UVM_INFO @ 10654054508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 70154084878565855572125807274184566340555505661873565888034120795387495102778 2140
UVM_INFO @ 1732374936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 60788918782224399880975257667733316299494195981885633918899532417661352667698 24648
UVM_INFO @ 2679783643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 11362281654628264604348867572649561084774466857720330625898776633487033528616 7056
UVM_INFO @ 858564319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 96895643151070805866005911311875849522059081830887643523739474760698576163614 217
UVM_INFO @ 364995551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112121047586196980464040130655307498858141356874431488738523668215913188196885 28979
UVM_INFO @ 1526397682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 110890639381870296112214475272096011666884454571562305829056516751851081686354 98
UVM_INFO @ 102288656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81694777069799266800130511334350784926753206949157535137405942638511799490417 11480
UVM_INFO @ 1727964950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10409649740042659268154998191439148802145744289690113640319790887955149080593 6622
UVM_INFO @ 22340201649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76052349753392928794102602063124972479347811712721282643844334946295928080065 1983
UVM_INFO @ 1009986460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 115653080437345795778722204325817817855562462791122324294301578027576288682782 12308
UVM_INFO @ 841858141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 32298938660928468279687201180729712915456946630731466920665379577752060271126 332
UVM_INFO @ 121442534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 11687613963461779636439761289431505533260739209328432577670765532017818722130 26699
UVM_INFO @ 3490601417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:764) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 11 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 83204699593232284912913120474809755008543767539142884033148311093701401552074 104
UVM_INFO @ 56036038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 32035843852319679250521810229031028712009882864454408806141104341694237449307 2151
UVM_INFO @ 1960640958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 41956266628458462814684509336010559280341793507634316697250409901794618329032 10445
UVM_INFO @ 15980180728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76968223270292752925322622254446469260926147338324469389501700218372443286064 957
UVM_INFO @ 658909711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95802683282478534215293519825041999829996973245778822025396874861161372323554 50523
UVM_INFO @ 25316557248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 40109457825734014286256159392090147762762414219800536307038503843917497866850 17118
UVM_INFO @ 6438136314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 99443543921384737511844358838666470470598139435123138465086301621635922527703 6876
UVM_INFO @ 9068353871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38684101881299866108859415804779606086083081716755500287849723875617101934223 166
UVM_INFO @ 256094524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 90038446224805454861383051241606574505393862563205147321738820295035088114818 10111
UVM_INFO @ 1594781004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114779903391829028616003498852102613729275756681478977514248026895368267522077 5179
UVM_INFO @ 5453282462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45898937787322468216412890569682637358707207947303667010245933318475606825024 327
UVM_INFO @ 943951677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1306) scoreboard [scoreboard] pwr_otp_idle output is * while expect * within * cycles 10 test runs
otp_ctrl_parallel_key_req 46033766164295416375227521580268084336238276778595301495165995267603875376555 2700
UVM_INFO @ 889274886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 106955424079195627186277667197302531275704634199978190994519775767787605516572 7372
UVM_INFO @ 388198623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 66732151635255526038991244005983332473607459097326882449890362934275000158868 31385
UVM_INFO @ 17070174865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_parallel_key_req 84544860711765910593485372922981855531516838971179294594044319309738905197838 1093
UVM_INFO @ 187057587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 103905190748985436508932989493244738848158053880457048932463660189061854971316 137759
UVM_INFO @ 191461516269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 66104740006453112679793593737759975357874180481012269524653990497830165625269 24540
UVM_INFO @ 1193606313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48795433765818243227457560805957368352955926716890309251040020793618323563288 4227
UVM_INFO @ 451841152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4084850213810550309746335565130343772439544999510864790432828775194401351670 1023
UVM_INFO @ 329777902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91248523831561999669887176856614090126806505320129770840089424118632708249734 3573
UVM_INFO @ 1920230644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1088414174424758963358113251264553190622076997018850392187111029606465579838 530
UVM_INFO @ 344284283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otp_ctrl_stress_all_with_rand_reset 6373991745470263148985591875170954081857499364257641932408167861405825315660 5370
UVM_INFO @ 8153155678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:419) scoreboard [scoreboard] Waited * cycles but did not see alert fatal_check_error. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
otp_ctrl_parallel_lc_esc 87976685923682685594017837267689251385083733648273610720319027052180095502209 1888
UVM_INFO @ 159445455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred! 1 test run
otp_ctrl_stress_all_with_rand_reset 77319438436847697004636519511546661716559022742781557230604511805279352611807 22445
UVM_INFO @ 11495672236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---