Simulation Results: pwrmgr

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.41 %
  • code
  • 97.54 %
  • assert
  • 98.69 %
  • func
  • 99.01 %
  • line
  • 99.09 %
  • branch
  • 96.38 %
  • cond
  • 96.61 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
95.65%
V2
91.24%
V2S
73.91%
V3
35.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 0.970s 26.222us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.820s 56.590us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 0.920s 38.369us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 3.840s 1435.545us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.110s 47.653us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
pwrmgr_csr_mem_rw_with_rand_reset 3600.041s 0.000us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 0.920s 38.369us 5 5 100.00
pwrmgr_csr_aliasing 1.110s 47.653us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 1.780s 257.459us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 1.780s 257.459us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 1.280s 38.747us 10 10 100.00
pwrmgr_lowpower_invalid 1.020s 187.091us 10 10 100.00
reset 15 20 75.00
pwrmgr_reset 2.270s 1000.000us 7 10 70.00
pwrmgr_reset_invalid 1.170s 90.811us 8 10 80.00
main_power_glitch_reset 7 10 70.00
pwrmgr_reset 2.270s 1000.000us 7 10 70.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.970s 299.393us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.320s 284.223us 10 10 100.00
disable_rom_integrity_check 9 10 90.00
pwrmgr_disable_rom_integrity_check 1.580s 1000.000us 9 10 90.00
stress_all 4 10 40.00
pwrmgr_stress_all 10800.057s 0.000us 4 10 40.00
intr_test 10 10 100.00
pwrmgr_intr_test 0.920s 21.639us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwrmgr_tl_errors 2.820s 102.942us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwrmgr_tl_errors 2.820s 102.942us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 0.820s 56.590us 1 1 100.00
pwrmgr_csr_rw 0.920s 38.369us 5 5 100.00
pwrmgr_csr_aliasing 1.110s 47.653us 1 1 100.00
pwrmgr_same_csr_outstanding 1.230s 172.892us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 0.820s 56.590us 1 1 100.00
pwrmgr_csr_rw 0.920s 38.369us 5 5 100.00
pwrmgr_csr_aliasing 1.110s 47.653us 1 1 100.00
pwrmgr_same_csr_outstanding 1.230s 172.892us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 7 30 23.33
pwrmgr_tl_intg_err 3600.051s 0.000us 5 25 20.00
pwrmgr_sec_cm 3600.051s 0.000us 2 5 40.00
prim_count_check 2 5 40.00
pwrmgr_sec_cm 3600.051s 0.000us 2 5 40.00
prim_fsm_check 2 5 40.00
pwrmgr_sec_cm 3600.051s 0.000us 2 5 40.00
sec_cm_bus_integrity 5 25 20.00
pwrmgr_tl_intg_err 3600.051s 0.000us 5 25 20.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.550s 851.001us 10 10 100.00
sec_cm_rom_ctrl_intersig_mubi 20 20 100.00
pwrmgr_wakeup_reset 1.970s 299.393us 10 10 100.00
pwrmgr_repeat_wakeup_reset 3.570s 827.789us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.270s 105.115us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 0.950s 30.294us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 2 5 40.00
pwrmgr_sec_cm 3600.051s 0.000us 2 5 40.00
sec_cm_fsm_sparse 2 5 40.00
pwrmgr_sec_cm 3600.051s 0.000us 2 5 40.00
sec_cm_fsm_terminal 2 5 40.00
pwrmgr_sec_cm 3600.051s 0.000us 2 5 40.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 1.000s 47.117us 10 10 100.00
sec_cm_main_pd_rst_local_esc 3 10 30.00
pwrmgr_glitch 3600.045s 0.000us 3 10 30.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.630s 226.470us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.920s 38.369us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 0.920s 38.369us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 5 10 50.00
pwrmgr_escalation_timeout 1.220s 106.775us 5 10 50.00
stress_all_with_rand_reset 2 10 20.00
pwrmgr_stress_all_with_rand_reset 3600.046s 0.000us 2 10 20.00

Error Messages

   Test seed line log context
Job timed out after * minutes 43 test runs
pwrmgr_glitch 77514201358590179714076536789760023013087761120316519199104954788155398446883 None
pwrmgr_tl_intg_err 56606169138771299757277988662770170930953238928135599827471633982604452872181 None
pwrmgr_sec_cm 113026127221792355160998820549424401600010674599337183822491688327003783529149 None
pwrmgr_stress_all 31622094134970666085612134195259540919989432563273567007127425732018865373375 None
pwrmgr_csr_mem_rw_with_rand_reset 58838107237610975979379244422218152168868291173010767150151892742518872044192 None
pwrmgr_glitch 702232018281975492794952537996041364187772314680561023000846607028639744154 None
pwrmgr_stress_all_with_rand_reset 102513420084703982278149992704829618346550699563117252864765962155184339344328 None
pwrmgr_glitch 47561638672529137751236929136274992298918154821840375828912703169173445484318 None
pwrmgr_tl_intg_err 82455396869999806832598288598648428303416964888621135222192752948632530886667 None
pwrmgr_sec_cm 74856899657790301056202400649714788969768782983116526692834510590746093216759 None
pwrmgr_stress_all_with_rand_reset 112882323724427509043210047090583976986782883051483253350229475932692151534588 None
pwrmgr_glitch 59963885810051293508083510138215974356729989675579375343645190878652065659213 None
pwrmgr_tl_intg_err 87073322096565414784370421020350706591802012488295818832868545430959276305147 None
pwrmgr_sec_cm 58020328463467416966079105713362289844393538974900037603648863959008298072129 None
pwrmgr_stress_all_with_rand_reset 35338277661053122930474684975562901557975451613947816341879574957590856363849 None
pwrmgr_tl_intg_err 85550364283289938134786910099028180879429805522008961062962902952085684601303 None
pwrmgr_stress_all_with_rand_reset 95070554812277757979715772022656653093539627976655920147201342739639747294699 None
pwrmgr_tl_intg_err 100616384331167510219597259441357871235384426646543306705710794506885292488729 None
pwrmgr_stress_all_with_rand_reset 37254520673591855668877140992894061037436720917070083074976650700412310571872 None
pwrmgr_glitch 37649834545756647535080831511721190633099978055384062121558053151886090171268 None
pwrmgr_stress_all_with_rand_reset 60302311269039356716176142851523441416999945421494801842948853359200990251630 None
pwrmgr_stress_all 85636639726580046468621401149646263716111595058154137874774488894556311914445 None
pwrmgr_glitch 48480197737450495289805982238759064412691315837263080640040890935057414719283 None
pwrmgr_tl_intg_err 35589865919177895154347094447242962272082106079283013890167291105422932614509 None
pwrmgr_stress_all_with_rand_reset 103384421016547883107226659679955247893693146250889573007235962099814665494585 None
pwrmgr_stress_all 114064303938748774728427321269741893445813260432945504612590834531372021143754 None
pwrmgr_glitch 90988404620759655522396849704603806889432301009627798230836393274807179801211 None
pwrmgr_tl_intg_err 13579867045217020284684972981648722183092995823993951161884490536360011319262 None
pwrmgr_tl_intg_err 85399524831135472005257578983339239998372286876883332953475293718771387336653 None
pwrmgr_stress_all_with_rand_reset 15438268781857290112965238772595000653934303412128620277137378579861451847671 None
pwrmgr_stress_all 93851452835171948952095211981106671531961141480183073183709175567046641454307 None
pwrmgr_tl_intg_err 49865852432344988586405721257542761009757617190901016560029230596667835608754 None
pwrmgr_tl_intg_err 74347115599847925493041190293423948195510226760712756075018741230809929014327 None
pwrmgr_tl_intg_err 3442592307932765018168364829306857403672763470410490819316165854993059339356 None
pwrmgr_tl_intg_err 112205962768055985307620503003443647258032051577840343747413406733517395738793 None
pwrmgr_tl_intg_err 51660257122892404086521761966250741426228104625339939976329251531901251877730 None
pwrmgr_tl_intg_err 15997787656790797763563505967986119605020710406363364407373858221085300139275 None
pwrmgr_tl_intg_err 54851330537784632767848435410869739140647458523557241794502396880353923095471 None
pwrmgr_tl_intg_err 87223612250157564275305234904962877871237489485670467381201734025529634768600 None
pwrmgr_tl_intg_err 77883292124951804579926035370693561733403929836017701976205154039443995206863 None
pwrmgr_tl_intg_err 15271137005743528776498790794651766156783414501372344711038948364250295839301 None
pwrmgr_tl_intg_err 498242766439483269856055886797468430360997260867363867992144723960708876007 None
pwrmgr_tl_intg_err 11081668611337122451493362313607153138771988180357915049946303165193646372919 None
Offending '((!clk_en) || status)' 5 test runs
pwrmgr_escalation_timeout 18934515476940475255079845315913132033343928973189387328013923162794014517587 85
UVM_ERROR @ 185554057 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 185554057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 77515154788127812004054038483246984737774511174870540406305078005205582622682 85
UVM_ERROR @ 100097289 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 100097289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 84523784727390748959072325356605271253463591431175564977079681823317971476544 85
UVM_ERROR @ 99083720 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 99083720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 65833523772080359270318274853643509795649577013094804842244302660683877143505 85
UVM_ERROR @ 100901460 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 100901460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 91031909646885609314459849284289314661141744486626851562589366189817038705410 85
UVM_ERROR @ 101462387 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 101462387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
pwrmgr_reset 4538671259396319664132464606911544554599795746897625193174514764518775029 160
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 4132229248568638484677340182296651199913109505151281957761528323915346351971 101
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 62296878679567688138063746248860216880918790932334605864157131859804081975801 92
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 107183977685958187041877398783559560459568531196219896539289105308113237903599 154
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 2 test runs
pwrmgr_stress_all 27819451947877363545057727520706559257583275606087520985432892176830408486473 135
UVM_INFO @ 10058012742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 70553402768430277505903109391913906381297367322560705707544934353502170446293 89
UVM_INFO @ 10044450165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitReleaseLcRst 1 test run
pwrmgr_reset_invalid 86183787576868095379177903389554600204016276259909362070752277724899664329996 115
UVM_INFO @ 80890511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitAckPwrUp 1 test run
pwrmgr_reset_invalid 69823958282665669643499032631046281091532267587764055457731768488766792355943 115
UVM_INFO @ 90811062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---