Simulation Results: rom_ctrl/192kb

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.40 %
  • code
  • 98.53 %
  • assert
  • 97.39 %
  • func
  • 99.28 %
  • line
  • 99.21 %
  • branch
  • 99.28 %
  • cond
  • 98.81 %
  • toggle
  • 95.34 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 30.530s 9905.212us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 49.470s 66.275us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 17.590s 57.292us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 17.150s 121.095us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 18.670s 100.654us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 18.590s 239.724us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 17.590s 57.292us 5 5 100.00
rom_ctrl_csr_aliasing 18.670s 100.654us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 12.250s 59.676us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 17.870s 59.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 17.110s 8.796us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 122.720s 22893.282us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 62.440s 2427.316us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 18.360s 49.256us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 36.200s 1031.747us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 36.200s 1031.747us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 49.470s 66.275us 1 1 100.00
rom_ctrl_csr_rw 17.590s 57.292us 5 5 100.00
rom_ctrl_csr_aliasing 18.670s 100.654us 1 1 100.00
rom_ctrl_same_csr_outstanding 23.470s 240.275us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 49.470s 66.275us 1 1 100.00
rom_ctrl_csr_rw 17.590s 57.292us 5 5 100.00
rom_ctrl_csr_aliasing 18.670s 100.654us 1 1 100.00
rom_ctrl_same_csr_outstanding 23.470s 240.275us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 1030.370s 32864.025us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 114.690s 7948.742us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 2922.040s 1094.797us 5 5 100.00
rom_ctrl_tl_intg_err 651.820s 330.022us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 2922.040s 1094.797us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 2922.040s 1094.797us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 1030.370s 32864.025us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 1030.370s 32864.025us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 1030.370s 32864.025us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 1030.370s 32864.025us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 1030.370s 32864.025us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 2922.040s 1094.797us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 2922.040s 1094.797us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 30.530s 9905.212us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 30.530s 9905.212us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 30.530s 9905.212us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 651.820s 330.022us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 1030.370s 32864.025us 20 20 100.00
rom_ctrl_kmac_err_chk 62.440s 2427.316us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 1030.370s 32864.025us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 1030.370s 32864.025us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 1030.370s 32864.025us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 114.690s 7948.742us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 2922.040s 1094.797us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 391.750s 24582.746us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 30012565601350816910507872000919619287164923019983647259789191909279445136112 85
UVM_INFO @ 42355087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 94437518855267040655909838558614839370607964467189622217495663534199200888652 85
UVM_INFO @ 8796290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---