Simulation Results: rv_timer

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.50 %
  • code
  • 94.66 %
  • assert
  • 98.73 %
  • func
  • 99.12 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
52.50%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 2.420s 1504.444us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.880s 55.713us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 0.880s 11.448us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.510s 52.119us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.040s 17.742us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.500s 123.782us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 0.880s 11.448us 5 5 100.00
rv_timer_csr_aliasing 1.040s 17.742us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 20 20 100.00
rv_timer_random_reset 17.940s 190783.557us 20 20 100.00
disabled 20 20 100.00
rv_timer_disabled 5.390s 3135.326us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 408.840s 243626.234us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 408.840s 243626.234us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 9.160s 3818.613us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 0.880s 14.604us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 0.890s 13.077us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 3.900s 896.403us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 3.900s 896.403us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 0.880s 55.713us 1 1 100.00
rv_timer_csr_rw 0.880s 11.448us 5 5 100.00
rv_timer_csr_aliasing 1.040s 17.742us 1 1 100.00
rv_timer_same_csr_outstanding 1.040s 47.234us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 0.880s 55.713us 1 1 100.00
rv_timer_csr_rw 0.880s 11.448us 5 5 100.00
rv_timer_csr_aliasing 1.040s 17.742us 1 1 100.00
rv_timer_same_csr_outstanding 1.040s 47.234us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 1.280s 87.194us 5 5 100.00
rv_timer_tl_intg_err 2.190s 1963.338us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 2.190s 1963.338us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 10 10.00
rv_timer_min 1.510s 459.015us 1 10 10.00
max_value 0 10 0.00
rv_timer_max 1.130s 119.041us 0 10 0.00
stress_all_with_rand_reset 20 20 100.00
rv_timer_stress_all_with_rand_reset 64.450s 28952.014us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 4458124895581169777361567524456922456228066441895084847045515860517469777911 81
UVM_INFO @ 99507763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 4409664386578354520711301014248003969803799260902900705463850023559793356277 82
UVM_INFO @ 180390059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 63484495641497421705438402154489025952017421163044429461931938332107015125127 82
UVM_INFO @ 171281131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 1927652505789837962464816856056052489804606656699218982820120639936865827976 81
UVM_INFO @ 169135509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 76535842879298678674034325432345838469769169015378672645643638203719866638982 81
UVM_INFO @ 255946158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 68935726655194558235749512829724392308996112620770588797412995058318936806234 81
UVM_INFO @ 85954841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 99099052487241363286796095238221932205794251083376723660343753832729475159781 81
UVM_INFO @ 477361938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 35625024468185159383985693136876461833726330225832915844861705364181683545253 81
UVM_INFO @ 43327827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 4026961438268820274537760529101252215826968225263391410154406360572055969768 81
UVM_INFO @ 59237796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:179) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 9 test runs
rv_timer_min 10937954271284772057632709363684459950344371231425393345946822455093432373112 82
UVM_INFO @ 213526272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 80115836164794342849008206227679994696783015350753354798899399261842599256783 81
UVM_INFO @ 122099705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 57449317744766623037952475046974858394148704122971407288155164374634755708392 82
UVM_INFO @ 110355071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 53941676357736376113635494947441073618675883111443944890928097169650564422449 81
UVM_INFO @ 65742519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 108734252667276666283713639897365547487527961653237395185274027584405293483693 81
UVM_INFO @ 53192989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 4654567698289310200164811378806767553768142222639125486654480863349948003846 82
UVM_INFO @ 71101910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 6403944715646205416171680787863430963276522036022537018587788124914172137871 85
UVM_INFO @ 1662260998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 103317488406472163817844132206628817772536846795288669326217404621263748182779 82
UVM_INFO @ 459015481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 34520168120033251948389782040040501829297969105714054161515306308587528227472 82
UVM_INFO @ 68627954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:342) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 49630433146206329074906890417250761157026857407343773019516712438967711211750 81
UVM_INFO @ 119041105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---