Simulation Results: spi_host

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.95 %
  • code
  • 91.30 %
  • assert
  • 96.79 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.90%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 76.000s 2284.252us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 38.582us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 55.171us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 275.734us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 61.710us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 33.817us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 55.171us 5 5 100.00
spi_host_csr_aliasing 2.000s 61.710us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 14.348us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 16.926us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 16.000s 26.942us 10 10 100.00
error_event_intr 29 30 96.67
spi_host_overflow_underflow 17.000s 220.289us 10 10 100.00
spi_host_error_cmd 2.000s 18.933us 10 10 100.00
spi_host_event 40.000s 10366.035us 9 10 90.00
clock_rate 10 10 100.00
spi_host_speed 8.000s 35.997us 10 10 100.00
speed 10 10 100.00
spi_host_speed 8.000s 35.997us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 8.000s 35.997us 10 10 100.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 619.000s 62627.818us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 22.000s 823.334us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 16.000s 120.824us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 8.000s 35.997us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 8.000s 35.997us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 76.000s 2284.252us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 76.000s 2284.252us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 117.000s 10789.240us 10 10 100.00
spien 10 10 100.00
spi_host_spien 22.000s 863.008us 10 10 100.00
stall 9 10 90.00
spi_host_status_stall 960.000s 1000000.000us 9 10 90.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 4.000s 167.259us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 17.000s 220.289us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 4.000s 39.055us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 78.072us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 5.000s 122.337us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 5.000s 122.337us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 38.582us 1 1 100.00
spi_host_csr_rw 2.000s 55.171us 5 5 100.00
spi_host_csr_aliasing 2.000s 61.710us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 53.040us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 38.582us 1 1 100.00
spi_host_csr_rw 2.000s 55.171us 5 5 100.00
spi_host_csr_aliasing 2.000s 61.710us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 53.040us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 264.458us 25 25 100.00
spi_host_sec_cm 2.000s 160.168us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 264.458us 25 25 100.00

Error Messages

   Test seed line log context
UVM_ERROR (spi_host_event_vseq.sv:45) [spi_host_event_vseq] Check failed txqd == spi_host_ctrl_reg.tx_watermark - i (* [*] vs * [*]) 1 test run
spi_host_event 61359146378628454415265874352119592923928142002253261081016342718226711061414 101
UVM_INFO @ 7135491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_status_stall 86923415841634868917795660404981604348240791845035877672042028377325876772666 8035
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---