| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
81.82% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 2918.790us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 27.391us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 62.234us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 4.000s | 214.629us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 2.000s | 45.881us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 5.000s | 733.277us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 62.234us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 45.881us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 347.000s | 111159.401us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 144.000s | 22652.750us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 72.000s | 80526.536us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 228.000s | 4464.048us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 241.000s | 63118.948us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 88.000s | 47070.262us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 91.000s | 67541.396us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 64.000s | 128465.032us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 7.000s | 681.083us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 321.000s | 29338.367us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 7.000s | 2783.345us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 8.000s | 4772.381us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 6.000s | 1685.477us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 20.000s | 2615.129us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 4.000s | 363.233us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 591.000s | 70010.462us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 6.000s | 44.381us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 309.334us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 309.334us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 27.391us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 62.234us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 45.881us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 59.607us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 27.391us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 62.234us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 45.881us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 59.607us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 35.000s | 14142.059us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 743.145us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 3.000s | 185.960us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 743.145us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 3.000s | 185.960us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 20.000s | 2615.129us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 20.000s | 2615.129us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 62.234us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 64.000s | 128465.032us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 64.000s | 128465.032us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 64.000s | 128465.032us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 91.000s | 67541.396us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 0 | 8 | 0.00 | |||
| sram_ctrl_mubi_enc_err | 3602.211s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 35.000s | 14142.059us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 0 | 8 | 0.00 | |||
| sram_ctrl_readback_err | 3602.092s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 2918.790us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 2918.790us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 64.000s | 128465.032us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 743.145us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 91.000s | 67541.396us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 743.145us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 743.145us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 2918.790us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 743.145us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 46.000s | 2206.870us | 8 | 8 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | 16 test runs | |||
| sram_ctrl_readback_err | 115460783598346241329187110804064575056890880038339034326501194084489226156663 | None | ||
| sram_ctrl_mubi_enc_err | 48083229951842994530450937937597553122208200145546325057104695485642201510649 | None | ||
| sram_ctrl_readback_err | 62653276704202949950427111444884077768146262333275607851137902969818208498338 | None | ||
| sram_ctrl_mubi_enc_err | 66595710593555463624509681506707023252422770309542012129794863469592806455395 | None | ||
| sram_ctrl_readback_err | 102903722529035099466844681611298829312564783693251360817651193328943317041739 | None | ||
| sram_ctrl_mubi_enc_err | 17274000689299834593647708796801518814230237789969850391605425570978007579772 | None | ||
| sram_ctrl_readback_err | 114190020238233034767004508650629399691201854575613977622946455994231480825794 | None | ||
| sram_ctrl_mubi_enc_err | 42081681875816395045328510094348526553279757344891939906048991896075084841033 | None | ||
| sram_ctrl_readback_err | 63908196817027900311967131394011257381351100613581938389656143814990835117991 | None | ||
| sram_ctrl_mubi_enc_err | 72357484776962213701422256485412425412713590519778238560353614721743152898055 | None | ||
| sram_ctrl_readback_err | 7021961827675482816279485530415129238394637169625477697268121156766051396986 | None | ||
| sram_ctrl_mubi_enc_err | 28035428659123542783862701724840672028751776430971819131128123911384796389690 | None | ||
| sram_ctrl_readback_err | 52921028636454076470115399244399903962632938092971867232300857407846956749546 | None | ||
| sram_ctrl_mubi_enc_err | 66462529504723445403092472905602421239117386331901323741340978612124342999707 | None | ||
| sram_ctrl_readback_err | 80042508979377016721164831127273081973080843039123611329027395683073541046536 | None | ||
| sram_ctrl_mubi_enc_err | 83460956278322673894495362566754527454004477397250694263008892532132923163752 | None | ||