| V1 |
|
97.30% |
| V2 |
|
100.00% |
| V2S |
|
81.82% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 55.380us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 44.447us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 12.694us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 2.000s | 202.989us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 2.000s | 21.718us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 4 | 5 | 80.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 2.000s | 37.619us | 4 | 5 | 80.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 12.694us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 21.718us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 12.000s | 1438.110us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 7.000s | 818.966us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 17.000s | 3619.093us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 286.000s | 38562.021us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 9.000s | 2204.823us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 19.000s | 11171.070us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 8.000s | 2666.607us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 18.000s | 13524.304us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 3.000s | 221.396us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 399.000s | 22567.105us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 2.000s | 169.219us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 2.000s | 42.894us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 2.000s | 73.587us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 15.000s | 620.689us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 2.000s | 95.880us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 52.000s | 2838.837us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 3.000s | 32.366us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 601.284us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 601.284us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 44.447us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 12.694us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 21.718us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 44.123us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 44.447us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 12.694us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 21.718us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 44.123us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 4.000s | 1664.488us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1183.705us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 5.000s | 849.912us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1183.705us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 5.000s | 849.912us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 15.000s | 620.689us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 15.000s | 620.689us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 12.694us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 18.000s | 13524.304us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 18.000s | 13524.304us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 18.000s | 13524.304us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 8.000s | 2666.607us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 0 | 8 | 0.00 | |||
| sram_ctrl_mubi_enc_err | 3601.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 4.000s | 1664.488us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 0 | 8 | 0.00 | |||
| sram_ctrl_readback_err | 3601.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 55.380us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 55.380us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 18.000s | 13524.304us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1183.705us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 8.000s | 2666.607us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1183.705us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1183.705us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 3.000s | 55.380us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 1183.705us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 73.000s | 3901.710us | 8 | 8 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | 16 test runs | |||
| sram_ctrl_readback_err | 9223670379328283663102709999938999953097760425748418458072568698755451327819 | None | ||
| sram_ctrl_mubi_enc_err | 60285322332386651087694591236860414824340313814531062903537979824876070191621 | None | ||
| sram_ctrl_readback_err | 85472537694593843838035661149483273153038248162661230806383093944375617114394 | None | ||
| sram_ctrl_mubi_enc_err | 106818032503068490708657281104702638019505173863979278412006146513479874587553 | None | ||
| sram_ctrl_readback_err | 51518370728799593223156837880612447146039850348600682939079024070271355177378 | None | ||
| sram_ctrl_mubi_enc_err | 46569580991226062021280892109811386779995514042747374205082950012968078571780 | None | ||
| sram_ctrl_readback_err | 56999485032847507354207749069441134960169494703137122038952184446764208022439 | None | ||
| sram_ctrl_mubi_enc_err | 69823969457074343478483654752031892533412213395825752041327063982633904079030 | None | ||
| sram_ctrl_readback_err | 48725425716214930660364859399251512128601904816360953582953788892737941156573 | None | ||
| sram_ctrl_mubi_enc_err | 16079206654245677783771905868286310399515787301769490288819649488031604439615 | None | ||
| sram_ctrl_readback_err | 23272412140043626384537094061851571098799547272325254669551059012667555247770 | None | ||
| sram_ctrl_mubi_enc_err | 28013565941852847402749457579901566988770162521617165048386800701393041289217 | None | ||
| sram_ctrl_readback_err | 17558803530912920277814847046741491727718364137317069729562542456471729520441 | None | ||
| sram_ctrl_mubi_enc_err | 7025486221268483172875754478882163619027719160433049673761539703045605340964 | None | ||
| sram_ctrl_readback_err | 25776594843417963794264063462590468612598396987781853266893450349804680649071 | None | ||
| sram_ctrl_mubi_enc_err | 61571236620292061678394591973797035639161251394595098454507111742516894881571 | None | ||
| UVM_ERROR (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * | 1 test run | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 17477052551786499246134209191990473300468050917957917866287016131024086330921 | 88 |
UVM_INFO @ 194955558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|