Simulation Results: uart

 
22/08/2026 09:08:29 DVSim: v1.49.0 sha: 34ceb5e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.78 %
  • code
  • 92.64 %
  • assert
  • 98.27 %
  • func
  • 99.44 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 98.25 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
97.48%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
uart_smoke 26.890s 6049.005us 10 10 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.880s 14.888us 1 1 100.00
csr_rw 5 5 100.00
uart_csr_rw 0.950s 19.390us 5 5 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.620s 47.291us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.980s 16.258us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
uart_csr_mem_rw_with_rand_reset 1.640s 131.095us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
uart_csr_rw 0.950s 19.390us 5 5 100.00
uart_csr_aliasing 0.980s 16.258us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 10 10 100.00
uart_tx_rx 72.790s 155352.803us 10 10 100.00
parity 20 20 100.00
uart_smoke 26.890s 6049.005us 10 10 100.00
uart_tx_rx 72.790s 155352.803us 10 10 100.00
parity_error 20 20 100.00
uart_intr 405.910s 296715.281us 10 10 100.00
uart_rx_parity_err 109.750s 170369.288us 10 10 100.00
watermark 20 20 100.00
uart_tx_rx 72.790s 155352.803us 10 10 100.00
uart_intr 405.910s 296715.281us 10 10 100.00
fifo_full 10 10 100.00
uart_fifo_full 113.730s 72208.935us 10 10 100.00
fifo_overflow 10 10 100.00
uart_fifo_overflow 151.300s 82111.827us 10 10 100.00
fifo_reset 200 200 100.00
uart_fifo_reset 930.380s 88369.334us 200 200 100.00
rx_frame_err 10 10 100.00
uart_intr 405.910s 296715.281us 10 10 100.00
rx_break_err 10 10 100.00
uart_intr 405.910s 296715.281us 10 10 100.00
rx_timeout 10 10 100.00
uart_intr 405.910s 296715.281us 10 10 100.00
perf 10 10 100.00
uart_perf 923.890s 26411.995us 10 10 100.00
sys_loopback 10 10 100.00
uart_loopback 12.880s 12149.144us 10 10 100.00
line_loopback 10 10 100.00
uart_loopback 12.880s 12149.144us 10 10 100.00
rx_noise_filter 2 10 20.00
uart_noise_filter 74.250s 153966.137us 2 10 20.00
rx_start_bit_filter 10 10 100.00
uart_rx_start_bit_filter 76.300s 42226.269us 10 10 100.00
tx_overide 10 10 100.00
uart_tx_ovrd 18.830s 6572.259us 10 10 100.00
rx_oversample 10 10 100.00
uart_rx_oversample 21.480s 6008.893us 10 10 100.00
long_b2b_transfer 10 10 100.00
uart_long_xfer_wo_dly 1242.140s 122211.279us 10 10 100.00
stress_all 8 10 80.00
uart_stress_all 1055.040s 391115.054us 8 10 80.00
alert_test 10 10 100.00
uart_alert_test 0.900s 36.159us 10 10 100.00
intr_test 10 10 100.00
uart_intr_test 0.930s 18.027us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
uart_tl_errors 2.830s 971.971us 25 25 100.00
tl_d_illegal_access 25 25 100.00
uart_tl_errors 2.830s 971.971us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
uart_csr_hw_reset 0.880s 14.888us 1 1 100.00
uart_csr_rw 0.950s 19.390us 5 5 100.00
uart_csr_aliasing 0.980s 16.258us 1 1 100.00
uart_same_csr_outstanding 1.080s 45.626us 5 5 100.00
tl_d_partial_access 12 12 100.00
uart_csr_hw_reset 0.880s 14.888us 1 1 100.00
uart_csr_rw 0.950s 19.390us 5 5 100.00
uart_csr_aliasing 0.980s 16.258us 1 1 100.00
uart_same_csr_outstanding 1.080s 45.626us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
uart_sec_cm 1.280s 129.597us 5 5 100.00
uart_tl_intg_err 1.710s 194.781us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
uart_tl_intg_err 1.710s 194.781us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
uart_stress_all_with_rand_reset 71.410s 14183.886us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 6 test runs
uart_noise_filter 45173604447809795869752037061792870088869723068696100792579943945261037712960 86
UVM_ERROR @ 7310890161 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 7310901655 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (61 [0x3d] vs 254 [0xfe]) reg name: uart_reg_block.rdata
UVM_ERROR @ 7310924643 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 7310936137 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (61 [0x3d] vs 255 [0xff]) reg name: uart_reg_block.rdata
uart_noise_filter 70122222679046648634089049802841113943541652940958559944148724148420680811229 84
UVM_ERROR @ 85432801282 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 85432844760 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (98 [0x62] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 85432931716 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 85432975194 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (98 [0x62] vs 238 [0xee]) reg name: uart_reg_block.rdata
uart_noise_filter 63431955604739902629711929754448700736364980314643371910660350910816305539295 84
UVM_ERROR @ 69340000448 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 69340231217 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 219 [0xdb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 69340385063 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 69340538909 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 247 [0xf7]) reg name: uart_reg_block.rdata
uart_stress_all 91524962406369919243774077936526677451319201549350989369625713436668794989742 121
UVM_ERROR @ 72238544550 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 72238659936 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (170 [0xaa] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 72238736860 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 72238852246 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (170 [0xaa] vs 255 [0xff]) reg name: uart_reg_block.rdata
uart_noise_filter 10568874289650094541738213929423372907301882740933411821407955226516722673369 83
UVM_ERROR @ 1177524174 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1177574679 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 1332715938 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 1332715938 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all_with_rand_reset 101561368375336968756584963856176510042966234714939089402503331390898744613997 106
UVM_ERROR @ 589793863 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 589804280 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 589835531 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 589845948 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 191 [0xbf]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:390) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 4 test runs
uart_stress_all 51006555111786313746798157164576778105714088324986103949169184139951938671369 116
UVM_ERROR @ 366762300592 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_INFO @ 367909820592 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 1/3
UVM_INFO @ 409833460592 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 2/3
UVM_INFO @ 446310420592 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 3/3
uart_noise_filter 50785111741557765556983428087992904247642029574368556743860060974910098319956 83
UVM_ERROR @ 2847771376 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 4114313611 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
UVM_ERROR @ 4114376110 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
UVM_ERROR @ 4114438609 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0, clk_pulses: 0
uart_noise_filter 102452620811300045104860097856027827032878736060692386291330441694838258069190 83
UVM_ERROR @ 15503299207 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 15902796810 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 12, clk_pulses: 0
UVM_ERROR @ 15902840288 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 15902862027 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 247 [0xf7]) reg name: uart_reg_block.rdata
uart_stress_all_with_rand_reset 76913017639306562370401053769949317443824909650833807939997018307873677161313 187
UVM_ERROR @ 3180249310 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3184979310 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3185249310 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 3185419310 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 2 test runs
uart_noise_filter 102071396464597441446616207705175518924364594464784160962846332454436613260093 80
UVM_ERROR @ 233348782 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 233348782 ps: (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 265440012 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 537488187 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
uart_noise_filter 18753195389517577275586511789477626743320236380910002775270875903264902046386 82
UVM_ERROR @ 4803485946 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 4937637431 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 4937679985 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 4937722539 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (80 [0x50] vs 255 [0xff]) reg name: uart_reg_block.rdata