Simulation Results: adc_ctrl

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 71.43 %
  • code
  • 98.00 %
  • assert
  • 96.92 %
  • func
  • 19.36 %
  • line
  • 99.05 %
  • branch
  • 98.51 %
  • cond
  • 95.12 %
  • toggle
  • 100.00 %
  • FSM
  • 97.30 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
adc_ctrl_smoke 18.970s 5706.155us 10 10 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.370s 579.825us 1 1 100.00
csr_rw 5 5 100.00
adc_ctrl_csr_rw 1.630s 495.390us 5 5 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 23.360s 23321.259us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.510s 445.158us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 2.500s 511.451us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
adc_ctrl_csr_rw 1.630s 495.390us 5 5 100.00
adc_ctrl_csr_aliasing 1.510s 445.158us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 10 10 100.00
adc_ctrl_filters_polled 142.550s 56043.937us 10 10 100.00
filters_polled_fixed 10 10 100.00
adc_ctrl_filters_polled_fixed 95.980s 34983.810us 10 10 100.00
filters_interrupt 10 10 100.00
adc_ctrl_filters_interrupt 92.820s 33286.405us 10 10 100.00
filters_interrupt_fixed 10 10 100.00
adc_ctrl_filters_interrupt_fixed 128.910s 55447.139us 10 10 100.00
filters_wakeup 10 10 100.00
adc_ctrl_filters_wakeup 118.810s 52520.323us 10 10 100.00
filters_wakeup_fixed 10 10 100.00
adc_ctrl_filters_wakeup_fixed 171.010s 75982.210us 10 10 100.00
filters_both 10 10 100.00
adc_ctrl_filters_both 131.640s 70113.357us 10 10 100.00
clock_gating 10 10 100.00
adc_ctrl_clock_gating 68.960s 69583.477us 10 10 100.00
poweron_counter 10 10 100.00
adc_ctrl_poweron_counter 14.660s 5525.760us 10 10 100.00
lowpower_counter 10 10 100.00
adc_ctrl_lowpower_counter 102.590s 43660.781us 10 10 100.00
fsm_reset 10 10 100.00
adc_ctrl_fsm_reset 296.040s 122890.247us 10 10 100.00
stress_all 10 10 100.00
adc_ctrl_stress_all 286.240s 230661.174us 10 10 100.00
alert_test 10 10 100.00
adc_ctrl_alert_test 2.160s 490.523us 10 10 100.00
intr_test 10 10 100.00
adc_ctrl_intr_test 2.130s 425.327us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
adc_ctrl_tl_errors 3.580s 510.005us 25 25 100.00
tl_d_illegal_access 25 25 100.00
adc_ctrl_tl_errors 3.580s 510.005us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
adc_ctrl_csr_hw_reset 2.370s 579.825us 1 1 100.00
adc_ctrl_csr_rw 1.630s 495.390us 5 5 100.00
adc_ctrl_csr_aliasing 1.510s 445.158us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.330s 2205.682us 5 5 100.00
tl_d_partial_access 12 12 100.00
adc_ctrl_csr_hw_reset 2.370s 579.825us 1 1 100.00
adc_ctrl_csr_rw 1.630s 495.390us 5 5 100.00
adc_ctrl_csr_aliasing 1.510s 445.158us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.330s 2205.682us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
adc_ctrl_sec_cm 17.550s 7747.342us 5 5 100.00
adc_ctrl_tl_intg_err 24.810s 8365.732us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
adc_ctrl_tl_intg_err 24.810s 8365.732us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
adc_ctrl_stress_all_with_rand_reset 22.620s 344640.222us 10 10 100.00