Simulation Results: aes/masked

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.43 %
  • code
  • 96.59 %
  • assert
  • 98.38 %
  • func
  • 97.32 %
  • block
  • 96.91 %
  • line
  • 97.77 %
  • branch
  • 92.75 %
  • toggle
  • 98.08 %
  • FSM
  • 97.78 %
Validation stages
V1
100.00%
V2
96.33%
V2S
91.12%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 70.856us 1 1 100.00
smoke 10 10 100.00
aes_smoke 8.000s 180.714us 10 10 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 61.283us 1 1 100.00
csr_rw 5 5 100.00
aes_csr_rw 2.000s 95.120us 5 5 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 644.087us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 104.481us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 124.656us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
aes_csr_rw 2.000s 95.120us 5 5 100.00
aes_csr_aliasing 3.000s 104.481us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 70 70 100.00
aes_smoke 8.000s 180.714us 10 10 100.00
aes_config_error 14.000s 872.077us 50 50 100.00
aes_stress 18.000s 1629.266us 10 10 100.00
key_length 70 70 100.00
aes_smoke 8.000s 180.714us 10 10 100.00
aes_config_error 14.000s 872.077us 50 50 100.00
aes_stress 18.000s 1629.266us 10 10 100.00
back2back 35 35 100.00
aes_stress 18.000s 1629.266us 10 10 100.00
aes_b2b 41.000s 716.774us 25 25 100.00
backpressure 10 10 100.00
aes_stress 18.000s 1629.266us 10 10 100.00
multi_message 94 95 98.95
aes_smoke 8.000s 180.714us 10 10 100.00
aes_config_error 14.000s 872.077us 50 50 100.00
aes_stress 18.000s 1629.266us 10 10 100.00
aes_alert_reset 52.000s 4222.608us 24 25 96.00
failure_test 84 85 98.82
aes_man_cfg_err 3.000s 130.297us 10 10 100.00
aes_config_error 14.000s 872.077us 50 50 100.00
aes_alert_reset 52.000s 4222.608us 24 25 96.00
trigger_clear_test 10 10 100.00
aes_clear 7.000s 108.296us 10 10 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 107.000s 6794.993us 1 1 100.00
reset_recovery 24 25 96.00
aes_alert_reset 52.000s 4222.608us 24 25 96.00
stress 10 10 100.00
aes_stress 18.000s 1629.266us 10 10 100.00
sideload 20 20 100.00
aes_stress 18.000s 1629.266us 10 10 100.00
aes_sideload 8.000s 141.223us 10 10 100.00
deinitialization 10 10 100.00
aes_deinit 5.000s 228.204us 10 10 100.00
stress_all 3 10 30.00
aes_stress_all 10805.000s 0.000us 3 10 30.00
alert_test 10 10 100.00
aes_alert_test 7.000s 126.038us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
aes_tl_errors 7.000s 3031.693us 25 25 100.00
tl_d_illegal_access 25 25 100.00
aes_tl_errors 7.000s 3031.693us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
aes_csr_hw_reset 2.000s 61.283us 1 1 100.00
aes_csr_rw 2.000s 95.120us 5 5 100.00
aes_csr_aliasing 3.000s 104.481us 1 1 100.00
aes_same_csr_outstanding 3.000s 75.203us 5 5 100.00
tl_d_partial_access 12 12 100.00
aes_csr_hw_reset 2.000s 61.283us 1 1 100.00
aes_csr_rw 2.000s 95.120us 5 5 100.00
aes_csr_aliasing 3.000s 104.481us 1 1 100.00
aes_same_csr_outstanding 3.000s 75.203us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 5 10 50.00
aes_reseed 48.000s 1813.751us 5 10 50.00
fault_inject 584 660 88.48
aes_fi 10.000s 166.298us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_cipher_fi 61.000s 0.000us 320 350 91.43
shadow_reg_update_error 19 20 95.00
aes_shadow_reg_errors 7.000s 238.134us 19 20 95.00
shadow_reg_read_clear_staged_value 19 20 95.00
aes_shadow_reg_errors 7.000s 238.134us 19 20 95.00
shadow_reg_storage_error 19 20 95.00
aes_shadow_reg_errors 7.000s 238.134us 19 20 95.00
shadowed_reset_glitch 19 20 95.00
aes_shadow_reg_errors 7.000s 238.134us 19 20 95.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 9.000s 159.455us 20 20 100.00
tl_intg_err 29 30 96.67
aes_sec_cm 6.000s 1498.847us 5 5 100.00
aes_tl_intg_err 9.000s 210.047us 24 25 96.00
sec_cm_bus_integrity 24 25 96.00
aes_tl_intg_err 9.000s 210.047us 24 25 96.00
sec_cm_lc_escalate_en_intersig_mubi 24 25 96.00
aes_alert_reset 52.000s 4222.608us 24 25 96.00
sec_cm_main_config_shadow 19 20 95.00
aes_shadow_reg_errors 7.000s 238.134us 19 20 95.00
sec_cm_gcm_config_shadow 19 20 95.00
aes_shadow_reg_errors 7.000s 238.134us 19 20 95.00
sec_cm_main_config_sparse 141 145 97.24
aes_smoke 8.000s 180.714us 10 10 100.00
aes_stress 18.000s 1629.266us 10 10 100.00
aes_alert_reset 52.000s 4222.608us 24 25 96.00
aes_core_fi 70.000s 10003.199us 97 100 97.00
sec_cm_gcm_config_sparse 157 160 98.12
aes_config_error 14.000s 872.077us 50 50 100.00
aes_stress 18.000s 1629.266us 10 10 100.00
aes_core_fi 70.000s 10003.199us 97 100 97.00
sec_cm_aux_config_shadow 19 20 95.00
aes_shadow_reg_errors 7.000s 238.134us 19 20 95.00
sec_cm_aux_config_regwen 20 20 100.00
aes_readability 8.000s 84.391us 10 10 100.00
aes_stress 18.000s 1629.266us 10 10 100.00
sec_cm_key_sideload 20 20 100.00
aes_stress 18.000s 1629.266us 10 10 100.00
aes_sideload 8.000s 141.223us 10 10 100.00
sec_cm_key_sw_unreadable 10 10 100.00
aes_readability 8.000s 84.391us 10 10 100.00
sec_cm_data_reg_sw_unreadable 10 10 100.00
aes_readability 8.000s 84.391us 10 10 100.00
sec_cm_key_sec_wipe 10 10 100.00
aes_readability 8.000s 84.391us 10 10 100.00
sec_cm_iv_config_sec_wipe 10 10 100.00
aes_readability 8.000s 84.391us 10 10 100.00
sec_cm_data_reg_sec_wipe 10 10 100.00
aes_readability 8.000s 84.391us 10 10 100.00
sec_cm_data_reg_key_sca 10 10 100.00
aes_stress 18.000s 1629.266us 10 10 100.00
sec_cm_key_masking 10 10 100.00
aes_stress 18.000s 1629.266us 10 10 100.00
sec_cm_main_fsm_sparse 0 10 0.00
aes_fi 10.000s 166.298us 0 10 0.00
sec_cm_main_fsm_redun 609 685 88.91
aes_fi 10.000s 166.298us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_cipher_fi 61.000s 0.000us 320 350 91.43
aes_ctr_fi 3.000s 71.530us 25 25 100.00
sec_cm_cipher_fsm_sparse 0 10 0.00
aes_fi 10.000s 166.298us 0 10 0.00
sec_cm_cipher_fsm_redun 584 660 88.48
aes_fi 10.000s 166.298us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_cipher_fi 61.000s 0.000us 320 350 91.43
sec_cm_cipher_ctr_redun 320 350 91.43
aes_cipher_fi 61.000s 0.000us 320 350 91.43
sec_cm_ctr_fsm_sparse 0 10 0.00
aes_fi 10.000s 166.298us 0 10 0.00
sec_cm_ctr_fsm_redun 289 335 86.27
aes_fi 10.000s 166.298us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_ctr_fi 3.000s 71.530us 25 25 100.00
sec_cm_ghash_fsm_sparse 0 10 0.00
aes_fi 10.000s 166.298us 0 10 0.00
sec_cm_ctrl_sparse 609 685 88.91
aes_fi 10.000s 166.298us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_cipher_fi 61.000s 0.000us 320 350 91.43
aes_ctr_fi 3.000s 71.530us 25 25 100.00
sec_cm_main_fsm_global_esc 24 25 96.00
aes_alert_reset 52.000s 4222.608us 24 25 96.00
sec_cm_main_fsm_local_esc 609 685 88.91
aes_fi 10.000s 166.298us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_cipher_fi 61.000s 0.000us 320 350 91.43
aes_ctr_fi 3.000s 71.530us 25 25 100.00
sec_cm_cipher_fsm_local_esc 609 685 88.91
aes_fi 10.000s 166.298us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_cipher_fi 61.000s 0.000us 320 350 91.43
aes_ctr_fi 3.000s 71.530us 25 25 100.00
sec_cm_ctr_fsm_local_esc 289 335 86.27
aes_fi 10.000s 166.298us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_ctr_fi 3.000s 71.530us 25 25 100.00
sec_cm_ghash_fsm_local_esc 0 10 0.00
aes_fi 10.000s 166.298us 0 10 0.00
sec_cm_data_reg_local_esc 584 660 88.48
aes_fi 10.000s 166.298us 0 10 0.00
aes_control_fi 61.000s 0.000us 264 300 88.00
aes_cipher_fi 61.000s 0.000us 320 350 91.43
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 86.000s 2232.192us 0 10 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 38 test runs
aes_control_fi 64904081677564937626331841670053211401273645620987512802523403868598585762439 None
aes_cipher_fi 114271812964364252354782616002654024523470915378364219925393990576437998961688 None
aes_stress_all 101893190615752836866311057606356730905098259269070646844665339905898528070621 None
aes_cipher_fi 46847381986589485280091389411331948202934526134140640847660488760108574571230 None
aes_stress_all 15958482719010677812849867942296766437240856340465727245600191124906363139987 None
aes_control_fi 6703315400353368596044376678568495690166076043373510453926147107708825965858 None
aes_control_fi 96320426817276181894395922266188954175064296183039264835388743997761454176221 None
aes_control_fi 30972352038260607601815389404195514234217382836286802530139361160093020343729 None
aes_cipher_fi 92344362771250373948999983474690902384788378925571642276077438497163788817362 None
aes_control_fi 49045883291240098233828700283176917012254093478601842353244715708330440621986 None
aes_control_fi 50513173452414845790470596540373301296220514293268828301999763825018266057555 None
aes_cipher_fi 88438569777360671525373101961001128474739089922584860129800301629546503539967 None
aes_control_fi 4552218993607723400420027528862028269577399006965663583859253819840256169990 None
aes_control_fi 26137766446402380876972087996408940447977436289747981876483410241383199775742 None
aes_control_fi 114315421144238157795146589378838806961166780058601470329049050240451034843009 None
aes_control_fi 21049780212639109233325715246989537640567182518956394354679723425759067611742 None
aes_control_fi 66092380582496643734932686336052611307895845723236606292289157259543575986446 None
aes_control_fi 83835879239738051940048626913327771547611598823549925080931602366766943746522 None
aes_cipher_fi 93137062455129366328656570403340136290241572929732388959200088897431896916336 None
aes_control_fi 31245718169632812380814090874282755339785995608157067292822170399944493860519 None
aes_cipher_fi 66661992441137174254732727980748885487937971611384909403262432937608119387606 None
aes_control_fi 5784179676768652277997644528083443278710442519956091519832726356816904398253 None
aes_cipher_fi 100222359571949194032531501625299141384903932439331647099132268820456431382640 None
aes_control_fi 113415713437683725359369277730946308219335148756194603536800324173807708429687 None
aes_control_fi 50241684885889433422847226460302763952793495715712613860504015475784508791407 None
aes_cipher_fi 105395640898987174183753760451628554722169908962370133831611377468166598715370 None
aes_control_fi 90066130503189303892940412031332644149874539230558387139068845787123468957538 None
aes_cipher_fi 14179998893480657905663261206204988279495569992187259322532844712615422108075 None
aes_control_fi 102913007882494481293269424086117571727890951031626663547500223736991052484231 None
aes_cipher_fi 17004494188916699311467341040263279290517362950600251056876849828960045291197 None
aes_control_fi 61550166465705869165959992831138678131843889124182153032464009343378063388441 None
aes_control_fi 30799153943957829579925546539207045637546794624786512232415992804529640110620 None
aes_control_fi 2319409342503490475321730731209896522086234287827722402729151436873373681177 None
aes_control_fi 92945773882018345836613133670466794654712035486329989239966313112283296562672 None
aes_control_fi 49662903269169382701233876692594343217170166113684227915023281363522703389089 None
aes_control_fi 73537110412979657238261189620850171378793572112711646751297980163991020928779 None
aes_control_fi 99316365251749100325828687891181883996714970809253050397479478385683711544594 None
aes_cipher_fi 24969425596783779685973121219976169228504145179941194850592674400481832757986 None
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 19 test runs
aes_cipher_fi 9713492197688209020846310690543017050282331263002967466067194125037006225544 142
UVM_INFO @ 10026118386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 25108834070832538841570327667473783948966494084274390464888228854014395363075 141
UVM_INFO @ 10013262429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 23458903047471933095660025327188156149609814322000346220907688229096256602308 143
UVM_INFO @ 10009273439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 26112444378171880775019404673494190167633735933782464380155917394767570741858 139
UVM_INFO @ 10009342960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 26709775096445375407199610108236828417156442330980351169774030682589045904776 140
UVM_INFO @ 10034860809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 2603713311575687741621561224955670337712372736931784726483965677549455689291 148
UVM_INFO @ 10012560225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 95481220119467449466579584453246454398561412765839993670907363326206086575887 151
UVM_INFO @ 10018747272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 8913315114375792807994359648676045564718578418600082168355299457841978338313 146
UVM_INFO @ 10009312393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 22403019698941132221362450120821648552172128772969339464219923049462228146931 143
UVM_INFO @ 10010504129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 99820412591044121229441609511133330012200919836895176276839224462901099509715 140
UVM_INFO @ 10025966953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 76940880701749107889773138709609020964584417212339046691538979972177076682827 144
UVM_INFO @ 10022426564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 109552014455206861714457264992303978443180088956324925399825400887493187562308 145
UVM_INFO @ 10005942436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 44883863405413572728944580157480392666086906711178914425906481716143496328224 154
UVM_INFO @ 10025952029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 103755143290334587666869618007289706605739258889949412079306295314003751095262 141
UVM_INFO @ 10021257981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 19176052128433953819790076200555861675593831389675827064797015702915508425801 142
UVM_INFO @ 10133550133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 42772437814172293442990698962074751849225459271450833931554209546979571671575 149
UVM_INFO @ 10015991327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 99434937316208673336942701340576388243128221623535622520154636703958940115138 147
UVM_INFO @ 10014695146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 38743442076636354816624351317188788708084568215781077846900092998044743417098 146
UVM_INFO @ 10020135391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 76994440349342501364988820110113766775780204155147922773966239370430960380605 154
UVM_INFO @ 10006363965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 14 test runs
aes_stress_all_with_rand_reset 75108516188520960237031733739256162815308599149230887777023795310759351300150 311
UVM_INFO @ 639739637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_reseed 105126836465886425288416018081868652567868845188793227502891486524806588958969 39671
UVM_INFO @ 1236432316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 64985469451233086214749620306485320872589469913244911103074027204896084485623 469
UVM_INFO @ 935387197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_reseed 72170920936020413401650946837284739981343006471819720418886018030120655563741 14732
UVM_INFO @ 753971740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 617307100108836386398111195389117916037788960549879409728475753860505053990 1323
UVM_INFO @ 2232191863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 84118836415883573972796169958411345602661521584981827716928005311569661644657 1394
UVM_INFO @ 60670757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_reseed 103426673445502694326292210690551236306380648607296003458613378910675685052267 3606
UVM_INFO @ 486945042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 16232262109733438338276865486579309802183644312711555210689723806334556505568 140
UVM_INFO @ 60485402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 26117034839847118941004630030056103697481687863244226162440610551923485689206 103152
UVM_INFO @ 1600007112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 71743089525607356935916871445297510169730699380407415233100596441520040756387 200
UVM_INFO @ 185614484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_reseed 33954398221932586243354825020071968593739504860218529649115067374401497009354 14316
UVM_INFO @ 46978359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 26206133976229364865367246905986698956413269930307250088906722308802406054618 67543
UVM_INFO @ 797526747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 32274585227752803085274823245512864308701655988113324873805113884106694347257 220
UVM_INFO @ 64451462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_reseed 108481461154742911468955114915032539251890375408688896401636806273114238791222 124088
UVM_INFO @ 1813750642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard] 12 test runs
aes_fi 74395751811949911474327462105787501674972206132687244089896832500610846182289 14919
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
aes_fi 27743475397792836302805492334320130183276111423318385118566169635322078847492 9873
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 2
----| Expected corrupted: 0
aes_stress_all 103909666600598010753101187210004737234762557585688253773016168904147500648599 44584
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 2
----| Seen: 1
----| Expected corrupted: 0
aes_fi 40244722356383027317919716465415860465092921151199200310831174169089029645203 16827
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
aes_fi 33806038835099245138014354678228613657671929036116251120633370395494408713232 17965
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
aes_stress_all 64150855766614562569621866111657147131712730139084811055219773067121715857851 198201
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 2
----| Seen: 1
----| Expected corrupted: 0
aes_fi 111930669674984214963527662248927219157162983181233273046323639092521492906122 8287
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
aes_fi 57670862997268402421115263790442775902279324878355544819503849792647261817572 31095
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 4
----| Expected corrupted: 0
aes_fi 3440337819033721060105431971960146664479859099898861085364650986789807559978 18593
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
aes_fi 94607810320883713727731301524095210926674212921570580771703221804929514634382 5201
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 1
----| Expected corrupted: 0
aes_fi 84534072843737601792942803586558289962069358898765560545809768817285672962556 17105
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
aes_fi 55250176069198888468106990257410241257488583890971728788451667697391001149625 8957
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 11 test runs
aes_control_fi 19412746246533950498005464997005092272353328640301649659928177107913679602650 141
UVM_INFO @ 10025367333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 93086911664214202277549744575949898019380593571220527285521412464671234765303 146
UVM_INFO @ 10074149915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 17878888909256702411336645365910713704370627938488650222419550563190414320831 144
UVM_INFO @ 10012932834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 37356913323957631243437039706181227884664961569035759925667176623525664219856 141
UVM_INFO @ 10019246806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 35483976884875730613494277776780793940634856511265758999952198466253099698872 144
UVM_INFO @ 10081154497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 110632613693330798404610275218113479861199471592495558047168252483522463549128 145
UVM_INFO @ 10011986147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 40872471784324247679857095800853341217692609143227204912036970552118986609425 143
UVM_INFO @ 10017324817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 102950704991141871586026167148678813920358311510242140426635689200772933953739 147
UVM_INFO @ 10058527553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 5547216991281586935139573276911123593306350082941292024921229892313105470910 139
UVM_INFO @ 10431548441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 110560653587354461109920203117837889662418346662921567206633851617028643451852 154
UVM_INFO @ 10016883906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 105328272000890374816383925291530602830847188968454640314217998036959675596591 152
UVM_INFO @ 10007517088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 4 test runs
aes_stress_all_with_rand_reset 30889408201697434896746919704284465294689125143188536629851523757571078269187 149
UVM_INFO @ 11965790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 3044568543184090754041218821691827947623293588392528690521122552589504006227 271
UVM_INFO @ 5385539207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 101798537400129844467592442039601320748614986833503589679155596740761999034372 591
UVM_INFO @ 998667598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 111130477124372209834217667671774676558019805859595819821846958068273246448463 150
UVM_INFO @ 4112070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 3 test runs
aes_core_fi 110048908079415175856637265482950424789734824020169661267012729941844741925338 143
UVM_INFO @ 10007995912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 50755286167184151033391020405515381757842149577310130152050965455667189151311 142
UVM_INFO @ 10016451751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 86191657646374112311625919716515953801188895967104602344723420745534557749008 150
UVM_INFO @ 10003198951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1113): Assertion AesModeValid has failed 1 test run
aes_alert_reset 1113652115866031720149294856935974873458984160658689566154381291150982635526 351
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 44586126 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 44586126 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 44586126 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 44586126 ps: (aes_core.sv:1113) [ASSERT FAILED] AesModeValid
UVM_ERROR (cip_base_vseq.sv:1059) virtual_sequencer [aes_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
aes_tl_intg_err 13929493636412404426473702587207500734208333370743937259662768986040702044508 109
UVM_INFO @ 49594151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block_extended.ctrl_shadowed reset value: * 1 test run
aes_shadow_reg_errors 87774060966718639715297253127840074461472079395051382965320813695963027535072 106
UVM_INFO @ 9148683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---