Simulation Results: chip

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.15 %
  • code
  • 77.28 %
  • assert
  • 97.34 %
  • func
  • 98.82 %
  • line
  • 93.98 %
  • branch
  • 94.34 %
  • cond
  • 92.69 %
  • toggle
  • 72.04 %
  • FSM
  • 33.33 %
Validation stages
V1
98.40%
V2
86.83%
V2S
83.33%
V3
79.49%
unmapped
13.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 9 9 100.00
chip_sw_example_rom 154.900s 2258.760us 3 3 100.00
chip_sw_example_manufacturer 354.920s 2831.789us 3 3 100.00
chip_sw_example_concurrency 386.720s 2696.523us 3 3 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 606.470s 7873.311us 1 1 100.00
csr_rw 5 5 100.00
chip_csr_rw 1192.510s 13111.515us 5 5 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 2194.020s 18687.897us 1 1 100.00
csr_aliasing 0 1 0.00
chip_csr_aliasing 10800.190s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 4 5 80.00
chip_csr_mem_rw_with_rand_reset 1497.230s 17923.340us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 5 6 83.33
chip_csr_aliasing 10800.190s 0.000us 0 1 0.00
chip_csr_rw 1192.510s 13111.515us 5 5 100.00
xbar_smoke 50 50 100.00
xbar_smoke 12.150s 243.192us 50 50 100.00
chip_sw_gpio_out 3 3 100.00
chip_sw_gpio 580.370s 4251.959us 3 3 100.00
chip_sw_gpio_in 3 3 100.00
chip_sw_gpio 580.370s 4251.959us 3 3 100.00
chip_sw_gpio_irq 3 3 100.00
chip_sw_gpio 580.370s 4251.959us 3 3 100.00
chip_sw_uart_tx_rx 5 5 100.00
chip_sw_uart_tx_rx 766.090s 4188.499us 5 5 100.00
chip_sw_uart_rx_overflow 20 20 100.00
chip_sw_uart_tx_rx 766.090s 4188.499us 5 5 100.00
chip_sw_uart_tx_rx_idx1 781.070s 4625.245us 5 5 100.00
chip_sw_uart_tx_rx_idx2 798.890s 4388.828us 5 5 100.00
chip_sw_uart_tx_rx_idx3 741.840s 4618.040us 5 5 100.00
chip_sw_uart_baud_rate 20 20 100.00
chip_sw_uart_rand_baudrate 3246.890s 12887.775us 20 20 100.00
chip_sw_uart_tx_rx_alt_clk_freq 10 10 100.00
chip_sw_uart_tx_rx_alt_clk_freq 3277.590s 13125.608us 5 5 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 1879.650s 13056.748us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 8 10 80.00
chip_padctrl_attributes 933.950s 11785.490us 8 10 80.00
chip_padctrl_attributes 8 10 80.00
chip_padctrl_attributes 933.950s 11785.490us 8 10 80.00
chip_sw_sleep_pin_mio_dio_val 3 3 100.00
chip_sw_sleep_pin_mio_dio_val 364.680s 3098.389us 3 3 100.00
chip_sw_sleep_pin_wake 0 3 0.00
chip_sw_sleep_pin_wake 384.100s 3347.812us 0 3 0.00
chip_sw_sleep_pin_retention 0 3 0.00
chip_sw_sleep_pin_retention 305.100s 2683.238us 0 3 0.00
chip_sw_tap_strap_sampling 20 20 100.00
chip_tap_straps_dev 1946.200s 16229.726us 5 5 100.00
chip_tap_straps_testunlock0 958.070s 8464.155us 5 5 100.00
chip_tap_straps_rma 624.490s 5140.658us 5 5 100.00
chip_tap_straps_prod 1862.940s 14836.704us 5 5 100.00
chip_sw_data_integrity 6 6 100.00
chip_sw_data_integrity_escalation 917.780s 5901.679us 6 6 100.00
chip_sw_instruction_integrity 6 6 100.00
chip_sw_data_integrity_escalation 917.780s 5901.679us 6 6 100.00
chip_sw_ast_clk_outputs 3 3 100.00
chip_sw_ast_clk_outputs 1209.430s 7852.142us 3 3 100.00
chip_sw_ast_clk_rst_inputs 0 3 0.00
chip_sw_ast_clk_rst_inputs 3703.420s 14714.156us 0 3 0.00
chip_sw_ast_sys_clk_jitter 24 24 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 5998.840s 20193.963us 3 3 100.00
chip_sw_aes_enc_jitter_en 400.250s 2539.729us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1239.000s 6068.221us 3 3 100.00
chip_sw_hmac_enc_jitter_en 386.620s 3178.952us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 2578.620s 9814.396us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 381.910s 2730.441us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 750.130s 5139.495us 3 3 100.00
chip_sw_clkmgr_jitter 320.110s 3114.884us 3 3 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 384.770s 3095.356us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 5 8 62.50
chip_sw_sensor_ctrl_alert 1352.620s 7027.001us 5 5 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 281.110s 2861.853us 0 3 0.00
chip_sw_sensor_ctrl_ast_status 3 3 100.00
chip_sw_sensor_ctrl_status 348.040s 2772.084us 3 3 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 0 3 0.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 281.110s 2861.853us 0 3 0.00
chip_sw_smoketest 48 48 100.00
chip_sw_aes_smoketest 405.840s 3300.029us 3 3 100.00
chip_sw_aon_timer_smoketest 421.510s 3569.633us 3 3 100.00
chip_sw_clkmgr_smoketest 377.990s 2746.881us 3 3 100.00
chip_sw_csrng_smoketest 348.060s 2632.727us 3 3 100.00
chip_sw_entropy_src_smoketest 1626.110s 6375.143us 3 3 100.00
chip_sw_gpio_smoketest 407.820s 3377.740us 3 3 100.00
chip_sw_hmac_smoketest 433.820s 3348.628us 3 3 100.00
chip_sw_kmac_smoketest 392.460s 2782.856us 3 3 100.00
chip_sw_otbn_smoketest 2530.220s 10384.433us 3 3 100.00
chip_sw_pwrmgr_smoketest 601.060s 6109.391us 3 3 100.00
chip_sw_pwrmgr_usbdev_smoketest 697.000s 5860.528us 3 3 100.00
chip_sw_rv_plic_smoketest 334.030s 2604.979us 3 3 100.00
chip_sw_rv_timer_smoketest 404.730s 3077.320us 3 3 100.00
chip_sw_rstmgr_smoketest 354.050s 2956.986us 3 3 100.00
chip_sw_sram_ctrl_smoketest 375.160s 3198.078us 3 3 100.00
chip_sw_uart_smoketest 365.130s 3031.135us 3 3 100.00
chip_sw_otp_smoketest 3 3 100.00
chip_sw_otp_ctrl_smoketest 360.650s 3031.601us 3 3 100.00
chip_sw_rom_functests 3 3 100.00
rom_keymgr_dpe_functest 756.300s 4555.968us 3 3 100.00
chip_sw_boot 0 3 0.00
chip_sw_uart_tx_rx_bootstrap 28800.197s 0.000us 0 3 0.00
chip_sw_secure_boot 2 3 66.67
rom_e2e_smoke 5140.290s 15396.813us 2 3 66.67
chip_sw_rom_raw_unlock 0 3 0.00
rom_raw_unlock 1991.940s 22245.556us 0 3 0.00
chip_sw_power_idle_load 3 3 100.00
chip_sw_power_idle_load 788.600s 4672.138us 3 3 100.00
chip_sw_power_sleep_load 2 3 66.67
chip_sw_power_sleep_load 539.500s 9778.612us 2 3 66.67
chip_sw_exit_test_unlocked_bootstrap 0 3 0.00
chip_sw_exit_test_unlocked_bootstrap 13200.198s 0.000us 0 3 0.00
tl_d_oob_addr_access 24 30 80.00
chip_tl_errors 3600.193s 0.000us 24 30 80.00
tl_d_illegal_access 24 30 80.00
chip_tl_errors 3600.193s 0.000us 24 30 80.00
tl_d_outstanding_access 9 12 75.00
chip_csr_aliasing 10800.190s 0.000us 0 1 0.00
chip_same_csr_outstanding 7200.172s 0.000us 3 5 60.00
chip_csr_hw_reset 606.470s 7873.311us 1 1 100.00
chip_csr_rw 1192.510s 13111.515us 5 5 100.00
tl_d_partial_access 9 12 75.00
chip_csr_aliasing 10800.190s 0.000us 0 1 0.00
chip_same_csr_outstanding 7200.172s 0.000us 3 5 60.00
chip_csr_hw_reset 606.470s 7873.311us 1 1 100.00
chip_csr_rw 1192.510s 13111.515us 5 5 100.00
xbar_base_random_sequence 50 50 100.00
xbar_random 103.730s 2243.670us 50 50 100.00
xbar_random_delay 300 300 100.00
xbar_smoke_zero_delays 7.680s 51.484us 50 50 100.00
xbar_smoke_large_delays 112.700s 9932.831us 50 50 100.00
xbar_smoke_slow_rsp 112.880s 6353.705us 50 50 100.00
xbar_random_zero_delays 50.260s 514.096us 50 50 100.00
xbar_random_large_delays 480.580s 42581.227us 50 50 100.00
xbar_random_slow_rsp 519.620s 31709.303us 50 50 100.00
xbar_unmapped_address 100 100 100.00
xbar_unmapped_addr 65.000s 1389.286us 50 50 100.00
xbar_error_and_unmapped_addr 60.260s 1140.581us 50 50 100.00
xbar_error_cases 100 100 100.00
xbar_error_random 100.950s 2236.141us 50 50 100.00
xbar_error_and_unmapped_addr 60.260s 1140.581us 50 50 100.00
xbar_all_access_same_device 100 100 100.00
xbar_access_same_device 164.420s 3277.334us 50 50 100.00
xbar_access_same_device_slow_rsp 1265.340s 84630.287us 50 50 100.00
xbar_all_hosts_use_same_source_id 50 50 100.00
xbar_same_source 84.290s 2415.401us 50 50 100.00
xbar_stress_all 100 100 100.00
xbar_stress_all 625.120s 13765.517us 50 50 100.00
xbar_stress_all_with_error 648.030s 15042.179us 50 50 100.00
xbar_stress_with_reset 100 100 100.00
xbar_stress_all_with_rand_reset 808.280s 14774.319us 50 50 100.00
xbar_stress_all_with_reset_error 961.230s 20433.061us 50 50 100.00
rom_e2e_smoke 2 3 66.67
rom_e2e_smoke 5140.290s 15396.813us 2 3 66.67
rom_e2e_shutdown_output 2 3 66.67
rom_e2e_shutdown_output 4539.160s 25512.506us 2 3 66.67
rom_e2e_shutdown_exception_c 3 3 100.00
rom_e2e_shutdown_exception_c 5312.200s 20727.589us 3 3 100.00
rom_e2e_boot_policy_valid 15 15 100.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 4099.710s 10734.859us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 5233.850s 16126.854us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 5039.800s 16055.887us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 4950.070s 16325.679us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 4973.790s 15036.027us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 4130.530s 11778.127us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 5351.310s 15693.407us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 5446.710s 15723.874us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 5351.450s 16448.056us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 5213.370s 15540.071us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 7130.500s 18225.354us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 8920.430s 24354.600us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 9072.970s 24623.760us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 9128.700s 24149.765us 1 1 100.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 8788.020s 25376.295us 1 1 100.00
rom_e2e_sigverify_always 15 15 100.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 7397.910s 24145.402us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 8986.740s 36890.032us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 8615.830s 28273.719us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 9309.340s 39394.892us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 7916.620s 25927.458us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 4847.610s 21873.471us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 4596.670s 18802.313us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 4372.090s 14921.018us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 5030.830s 20648.709us 1 1 100.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 4675.830s 17975.251us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 4534.870s 15887.742us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 5366.680s 21812.067us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 4790.840s 14816.563us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 5115.530s 22039.321us 1 1 100.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 4921.270s 22179.579us 1 1 100.00
rom_e2e_asm_init 15 15 100.00
rom_e2e_asm_init_test_unlocked0 4431.120s 12637.877us 3 3 100.00
rom_e2e_asm_init_dev 5398.940s 16322.459us 3 3 100.00
rom_e2e_asm_init_prod 5479.590s 15421.859us 3 3 100.00
rom_e2e_asm_init_prod_end 5357.280s 16123.749us 3 3 100.00
rom_e2e_asm_init_rma 5221.830s 15562.669us 3 3 100.00
rom_e2e_keymgr_dpe_init 9 9 100.00
rom_e2e_keymgr_dpe_init_rom_ext_meas 9683.970s 30470.411us 3 3 100.00
rom_e2e_keymgr_dpe_init_rom_ext_no_meas 9600.540s 29677.689us 3 3 100.00
rom_e2e_keymgr_dpe_init_rom_ext_invalid_meas 9676.490s 29813.723us 3 3 100.00
rom_e2e_static_critical 3 3 100.00
rom_e2e_static_critical 5316.680s 17453.634us 3 3 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.194s 0.000us 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 3 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.194s 0.000us 0 3 0.00
chip_sw_aes_enc 6 6 100.00
chip_sw_aes_enc 413.990s 2795.472us 3 3 100.00
chip_sw_aes_enc_jitter_en 400.250s 2539.729us 3 3 100.00
chip_sw_aes_entropy 3 3 100.00
chip_sw_aes_entropy 363.110s 2598.218us 3 3 100.00
chip_sw_aes_idle 3 3 100.00
chip_sw_aes_idle 388.020s 2944.379us 3 3 100.00
chip_sw_aes_sideload 3 3 100.00
chip_sw_keymgr_dpe_sideload_aes 2850.730s 11264.756us 3 3 100.00
chip_sw_alert_handler_alerts 0 3 0.00
chip_sw_alert_test 366.780s 3285.307us 0 3 0.00
chip_sw_alert_handler_escalations 3 3 100.00
chip_sw_alert_handler_escalation 737.070s 5151.628us 3 3 100.00
chip_sw_all_escalation_resets 89 100 89.00
chip_sw_all_escalation_resets 902.200s 5446.073us 89 100 89.00
chip_sw_alert_handler_irqs 9 9 100.00
chip_plic_all_irqs_0 992.520s 4517.779us 3 3 100.00
chip_plic_all_irqs_10 572.420s 3846.236us 3 3 100.00
chip_plic_all_irqs_20 724.650s 4222.890us 3 3 100.00
chip_sw_alert_handler_entropy 0 3 0.00
chip_sw_alert_handler_entropy 427.300s 2788.279us 0 3 0.00
chip_sw_alert_handler_crashdump 2 3 66.67
chip_sw_rstmgr_alert_info 1835.730s 14173.305us 2 3 66.67
chip_sw_alert_handler_ping_timeout 3 3 100.00
chip_sw_alert_handler_ping_timeout 752.160s 5202.676us 3 3 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 380.640s 2877.383us 0 90 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 3 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 401.660s 2684.302us 0 3 0.00
chip_sw_alert_handler_lpg_clock_off 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 1584.250s 7607.907us 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 2068.550s 7751.718us 3 3 100.00
chip_sw_alert_handler_ping_ok 3 3 100.00
chip_sw_alert_handler_ping_ok 1676.020s 7728.435us 3 3 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 0 3 0.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 14400.203s 0.000us 0 3 0.00
chip_sw_aon_timer_wakeup_irq 3 3 100.00
chip_sw_aon_timer_irq 567.920s 4047.140us 3 3 100.00
chip_sw_aon_timer_sleep_wakeup 3 3 100.00
chip_sw_pwrmgr_smoketest 601.060s 6109.391us 3 3 100.00
chip_sw_aon_timer_wdog_bark_irq 3 3 100.00
chip_sw_aon_timer_irq 567.920s 4047.140us 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 1131.440s 8835.111us 3 3 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 3 3 100.00
chip_sw_aon_timer_wdog_bite_reset 1131.440s 8835.111us 3 3 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 5 5 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 662.020s 6953.991us 5 5 100.00
chip_sw_aon_timer_wdog_lc_escalate 3 3 100.00
chip_sw_aon_timer_wdog_lc_escalate 806.440s 4958.598us 3 3 100.00
chip_sw_clkmgr_idle_trans 12 12 100.00
chip_sw_otbn_randomness 1197.320s 5513.496us 3 3 100.00
chip_sw_aes_idle 388.020s 2944.379us 3 3 100.00
chip_sw_hmac_enc_idle 453.950s 3148.642us 3 3 100.00
chip_sw_kmac_idle 339.720s 3297.114us 3 3 100.00
chip_sw_clkmgr_off_trans 12 12 100.00
chip_sw_clkmgr_off_aes_trans 554.670s 3534.175us 3 3 100.00
chip_sw_clkmgr_off_hmac_trans 500.930s 3783.190us 3 3 100.00
chip_sw_clkmgr_off_kmac_trans 636.570s 4210.892us 3 3 100.00
chip_sw_clkmgr_off_otbn_trans 688.040s 3825.518us 3 3 100.00
chip_sw_clkmgr_off_peri 3 3 100.00
chip_sw_clkmgr_off_peri 1726.180s 11175.085us 3 3 100.00
chip_sw_clkmgr_div 21 21 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 750.860s 4084.471us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 802.000s 4772.028us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 836.280s 4529.137us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 787.790s 4987.397us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 846.120s 3897.269us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 779.590s 4630.099us 3 3 100.00
chip_sw_ast_clk_outputs 1209.430s 7852.142us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 2522.270s 20456.837us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw 6 6 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 836.280s 4529.137us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 787.790s 4987.397us 3 3 100.00
chip_sw_clkmgr_jitter 24 24 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 5998.840s 20193.963us 3 3 100.00
chip_sw_aes_enc_jitter_en 400.250s 2539.729us 3 3 100.00
chip_sw_edn_entropy_reqs_jitter 1239.000s 6068.221us 3 3 100.00
chip_sw_hmac_enc_jitter_en 386.620s 3178.952us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 2578.620s 9814.396us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 381.910s 2730.441us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 750.130s 5139.495us 3 3 100.00
chip_sw_clkmgr_jitter 320.110s 3114.884us 3 3 100.00
chip_sw_clkmgr_extended_range 24 24 100.00
chip_sw_clkmgr_jitter_reduced_freq 311.280s 3046.417us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 6467.600s 25621.554us 3 3 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 357.710s 3076.900us 3 3 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 409.620s 3397.698us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq 1653.750s 9508.047us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 417.300s 3633.106us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 728.370s 4677.982us 3 3 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 22902.500s 133327.899us 3 3 100.00
chip_sw_clkmgr_deep_sleep_frequency 3 3 100.00
chip_sw_ast_clk_outputs 1209.430s 7852.142us 3 3 100.00
chip_sw_clkmgr_sleep_frequency 0 3 0.00
chip_sw_clkmgr_sleep_frequency 742.150s 4194.330us 0 3 0.00
chip_sw_clkmgr_reset_frequency 0 3 0.00
chip_sw_clkmgr_reset_frequency 993.370s 11022.049us 0 3 0.00
chip_sw_clkmgr_escalation_reset 89 100 89.00
chip_sw_all_escalation_resets 902.200s 5446.073us 89 100 89.00
chip_sw_clkmgr_alert_handler_clock_enables 3 3 100.00
chip_sw_alert_handler_lpg_clkoff 1584.250s 7607.907us 3 3 100.00
chip_sw_csrng_edn_cmd 3 3 100.00
chip_sw_entropy_src_csrng 3104.280s 24097.573us 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read 3 3 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 566.050s 3947.232us 3 3 100.00
chip_sw_csrng_lc_hw_debug_en 3 3 100.00
chip_sw_csrng_lc_hw_debug_en_test 1269.120s 8375.400us 3 3 100.00
chip_sw_csrng_known_answer_tests 3 3 100.00
chip_sw_csrng_kat_test 399.940s 3050.884us 3 3 100.00
chip_sw_edn_entropy_reqs 16 16 100.00
chip_sw_csrng_edn_concurrency 8612.020s 32307.946us 10 10 100.00
chip_sw_entropy_src_ast_rng_req 386.890s 2587.921us 3 3 100.00
chip_sw_edn_entropy_reqs 1653.920s 7480.613us 3 3 100.00
chip_sw_entropy_src_ast_rng_req 3 3 100.00
chip_sw_entropy_src_ast_rng_req 386.890s 2587.921us 3 3 100.00
chip_sw_entropy_src_csrng 3 3 100.00
chip_sw_entropy_src_csrng 3104.280s 24097.573us 3 3 100.00
chip_sw_entropy_src_known_answer_tests 3 3 100.00
chip_sw_entropy_src_kat_test 372.560s 2683.277us 3 3 100.00
chip_sw_hmac_enc 6 6 100.00
chip_sw_hmac_enc 380.330s 3400.618us 3 3 100.00
chip_sw_hmac_enc_jitter_en 386.620s 3178.952us 3 3 100.00
chip_sw_hmac_idle 3 3 100.00
chip_sw_hmac_enc_idle 453.950s 3148.642us 3 3 100.00
chip_sw_hmac_all_configurations 3 3 100.00
chip_sw_hmac_oneshot 2675.030s 10395.908us 3 3 100.00
chip_sw_hmac_multistream_mode 0 3 0.00
chip_sw_hmac_multistream 3600.175s 0.000us 0 3 0.00
chip_sw_i2c_host_tx_rx 9 9 100.00
chip_sw_i2c_host_tx_rx 964.670s 5854.612us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx1 785.060s 5021.035us 3 3 100.00
chip_sw_i2c_host_tx_rx_idx2 787.610s 5297.068us 3 3 100.00
chip_sw_i2c_device_tx_rx 3 3 100.00
chip_sw_i2c_device_tx_rx 622.810s 3808.123us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 6 6 100.00
chip_sw_keymgr_dpe_key_derivation 2111.390s 9434.918us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_jitter_en 2578.620s 9814.396us 3 3 100.00
chip_sw_keymgr_dpe_sideload_kmac 3 3 100.00
chip_sw_keymgr_dpe_sideload_kmac 2319.830s 9681.680us 3 3 100.00
chip_sw_keymgr_dpe_sideload_aes 3 3 100.00
chip_sw_keymgr_dpe_sideload_aes 2850.730s 11264.756us 3 3 100.00
chip_sw_keymgr_dpe_sideload_otbn 0 3 0.00
chip_sw_keymgr_dpe_sideload_otbn 3600.199s 0.000us 0 3 0.00
chip_sw_kmac_enc 9 9 100.00
chip_sw_kmac_mode_cshake 339.480s 2921.885us 3 3 100.00
chip_sw_kmac_mode_kmac 435.750s 3201.863us 3 3 100.00
chip_sw_kmac_mode_kmac_jitter_en 381.910s 2730.441us 3 3 100.00
chip_sw_kmac_app_keymgr_dpe 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 2111.390s 9434.918us 3 3 100.00
chip_sw_kmac_app_lc 13 15 86.67
chip_sw_lc_ctrl_transition 3038.620s 25098.393us 13 15 86.67
chip_sw_kmac_app_rom 3 3 100.00
chip_sw_kmac_app_rom 752.070s 7031.508us 3 3 100.00
chip_sw_kmac_entropy 3 3 100.00
chip_sw_kmac_entropy 1954.370s 7861.576us 3 3 100.00
chip_sw_kmac_idle 3 3 100.00
chip_sw_kmac_idle 339.720s 3297.114us 3 3 100.00
chip_sw_lc_ctrl_alert_handler_escalation 3 3 100.00
chip_sw_alert_handler_escalation 737.070s 5151.628us 3 3 100.00
chip_sw_lc_ctrl_jtag_access 15 15 100.00
chip_tap_straps_dev 1946.200s 16229.726us 5 5 100.00
chip_tap_straps_rma 624.490s 5140.658us 5 5 100.00
chip_tap_straps_prod 1862.940s 14836.704us 5 5 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 362.190s 3083.607us 3 3 100.00
chip_sw_lc_ctrl_init 13 15 86.67
chip_sw_lc_ctrl_transition 3038.620s 25098.393us 13 15 86.67
chip_sw_lc_ctrl_transitions 13 15 86.67
chip_sw_lc_ctrl_transition 3038.620s 25098.393us 13 15 86.67
chip_sw_lc_ctrl_kmac_req 13 15 86.67
chip_sw_lc_ctrl_transition 3038.620s 25098.393us 13 15 86.67
chip_sw_lc_ctrl_key_div 3 3 100.00
chip_sw_keymgr_dpe_key_derivation_prod 3524.710s 13471.189us 3 3 100.00
chip_sw_lc_ctrl_broadcast 70 81 86.42
chip_sw_rram_rma_unlocked 743.370s 10010.340us 0 3 0.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 524.390s 3810.088us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 1211.910s 6744.981us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 1110.440s 5749.320us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 1025.710s 6994.201us 0 3 0.00
chip_sw_lc_ctrl_transition 3038.620s 25098.393us 13 15 86.67
chip_sw_rram_ctrl_lc_rw_en 839.960s 5247.741us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 2111.390s 9434.918us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 1713.730s 22725.171us 3 3 100.00
chip_sw_sram_ctrl_execution_main 1207.770s 7973.684us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_lc 2522.270s 20456.837us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 750.860s 4084.471us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 802.000s 4772.028us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 836.280s 4529.137us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 787.790s 4987.397us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 846.120s 3897.269us 3 3 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 779.590s 4630.099us 3 3 100.00
chip_tap_straps_dev 1946.200s 16229.726us 5 5 100.00
chip_tap_straps_rma 624.490s 5140.658us 5 5 100.00
chip_tap_straps_prod 1862.940s 14836.704us 5 5 100.00
chip_rv_dm_lc_disabled 240.290s 5217.181us 0 3 0.00
chip_lc_scrap 4 6 66.67
chip_sw_lc_ctrl_rma_to_scrap 725.780s 5591.735us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 914.060s 11109.561us 0 1 0.00
chip_sw_lc_ctrl_test_locked0_to_scrap 683.460s 6719.294us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 850.670s 9124.893us 2 3 66.67
chip_lc_test_locked 0 6 0.00
chip_sw_lc_walkthrough_testunlocks 3600.198s 0.000us 0 3 0.00
chip_rv_dm_lc_disabled 240.290s 5217.181us 0 3 0.00
chip_sw_lc_walkthrough 3 15 20.00
chip_sw_lc_walkthrough_dev 2247.040s 16403.990us 0 3 0.00
chip_sw_lc_walkthrough_prod 2539.080s 21397.933us 0 3 0.00
chip_sw_lc_walkthrough_prodend 2327.540s 19292.589us 3 3 100.00
chip_sw_lc_walkthrough_rma 1643.710s 15258.329us 0 3 0.00
chip_sw_lc_walkthrough_testunlocks 3600.198s 0.000us 0 3 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 8 9 88.89
chip_sw_lc_ctrl_volatile_raw_unlock 323.380s 5848.237us 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 423.100s 6310.121us 2 3 66.67
rom_volatile_raw_unlock 471.850s 5463.977us 3 3 100.00
chip_sw_otbn_op 6 6 100.00
chip_sw_otbn_ecdsa_op_irq 5766.490s 17187.983us 3 3 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 5998.840s 20193.963us 3 3 100.00
chip_sw_otbn_rnd_entropy 3 3 100.00
chip_sw_otbn_randomness 1197.320s 5513.496us 3 3 100.00
chip_sw_otbn_urnd_entropy 3 3 100.00
chip_sw_otbn_randomness 1197.320s 5513.496us 3 3 100.00
chip_sw_otbn_idle 3 3 100.00
chip_sw_otbn_randomness 1197.320s 5513.496us 3 3 100.00
chip_sw_otbn_mem_scramble 3 3 100.00
chip_sw_otbn_mem_scramble 677.670s 3990.966us 3 3 100.00
chip_otp_ctrl_init 13 15 86.67
chip_sw_lc_ctrl_transition 3038.620s 25098.393us 13 15 86.67
chip_sw_otp_ctrl_keys 9 12 75.00
chip_sw_otbn_mem_scramble 677.670s 3990.966us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 2111.390s 9434.918us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 705.140s 4539.930us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 3600.197s 0.000us 0 3 0.00
chip_sw_otp_ctrl_entropy 9 12 75.00
chip_sw_otbn_mem_scramble 677.670s 3990.966us 3 3 100.00
chip_sw_keymgr_dpe_key_derivation 2111.390s 9434.918us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access 705.140s 4539.930us 3 3 100.00
chip_sw_rv_core_ibex_icache_invalidate 3600.197s 0.000us 0 3 0.00
chip_sw_otp_ctrl_program 13 15 86.67
chip_sw_lc_ctrl_transition 3038.620s 25098.393us 13 15 86.67
chip_sw_otp_ctrl_program_error 3 3 100.00
chip_sw_lc_ctrl_program_error 887.950s 5648.162us 3 3 100.00
chip_sw_otp_ctrl_hw_cfg0 3 3 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 362.190s 3083.607us 3 3 100.00
chip_sw_otp_ctrl_lc_signals 22 27 81.48
chip_sw_otp_ctrl_lc_signals_test_unlocked0 524.390s 3810.088us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_dev 1211.910s 6744.981us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_prod 1110.440s 5749.320us 3 3 100.00
chip_sw_otp_ctrl_lc_signals_rma 1025.710s 6994.201us 0 3 0.00
chip_sw_lc_ctrl_transition 3038.620s 25098.393us 13 15 86.67
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1548.120s 7099.486us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 642.940s 6524.649us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 337.510s 3190.923us 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 342.810s 2685.970us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 890.070s 8219.530us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 0 3 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 658.670s 4763.076us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1522.800s 19659.236us 3 3 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 5 6 83.33
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1288.680s 11957.512us 2 3 66.67
chip_sw_aon_timer_wdog_bite_reset 1131.440s 8835.111us 3 3 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 0 3 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 382.930s 3496.221us 0 3 0.00
chip_sw_pwrmgr_wdog_reset 3 3 100.00
chip_sw_pwrmgr_wdog_reset 738.880s 4401.447us 3 3 100.00
chip_sw_pwrmgr_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_full_aon_reset 642.940s 6524.649us 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_main_power_glitch_reset 563.860s 4284.487us 3 3 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 440.810s 3707.709us 0 3 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 3 3 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 673.940s 6521.801us 3 3 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 3 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 308.000s 2271.071us 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 3 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 776.380s 7751.266us 0 3 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1227.020s 6845.607us 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 2040.270s 10646.171us 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 3 3 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2666.590s 23626.933us 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 3 3 100.00
chip_sw_pwrmgr_sleep_disabled 363.410s 2651.936us 3 3 100.00
chip_sw_pwrmgr_escalation_reset 89 100 89.00
chip_sw_all_escalation_resets 902.200s 5446.073us 89 100 89.00
chip_sw_rom_access 3 3 100.00
chip_sw_rom_ctrl_integrity_check 1713.730s 22725.171us 3 3 100.00
chip_sw_rom_ctrl_integrity_check 3 3 100.00
chip_sw_rom_ctrl_integrity_check 1713.730s 22725.171us 3 3 100.00
chip_sw_rstmgr_non_sys_reset_info 9 12 75.00
chip_sw_pwrmgr_all_reset_reqs 2040.270s 10646.171us 3 3 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 776.380s 7751.266us 0 3 0.00
chip_sw_pwrmgr_wdog_reset 738.880s 4401.447us 3 3 100.00
chip_sw_pwrmgr_smoketest 601.060s 6109.391us 3 3 100.00
chip_sw_rstmgr_sys_reset_info 3 3 100.00
chip_rv_dm_ndm_reset_req 576.670s 5196.957us 3 3 100.00
chip_sw_rstmgr_cpu_info 3 3 100.00
chip_sw_rstmgr_cpu_info 899.330s 6221.429us 3 3 100.00
chip_sw_rstmgr_sw_req_reset 3 3 100.00
chip_sw_rstmgr_sw_req 619.920s 4438.082us 3 3 100.00
chip_sw_rstmgr_alert_info 2 3 66.67
chip_sw_rstmgr_alert_info 1835.730s 14173.305us 2 3 66.67
chip_sw_rstmgr_sw_rst 3 3 100.00
chip_sw_rstmgr_sw_rst 372.120s 2956.543us 3 3 100.00
chip_sw_rstmgr_escalation_reset 89 100 89.00
chip_sw_all_escalation_resets 902.200s 5446.073us 89 100 89.00
chip_sw_rstmgr_alert_handler_reset_enables 3 3 100.00
chip_sw_alert_handler_lpg_reset_toggle 2068.550s 7751.718us 3 3 100.00
chip_sw_nmi_irq 3 3 100.00
chip_sw_rv_core_ibex_nmi_irq 943.140s 4384.823us 3 3 100.00
chip_sw_rv_core_ibex_rnd 3 3 100.00
chip_sw_rv_core_ibex_rnd 975.990s 4979.223us 3 3 100.00
chip_sw_rv_core_ibex_address_translation 3 3 100.00
chip_sw_rv_core_ibex_address_translation 433.950s 3015.306us 3 3 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 0 3 0.00
chip_sw_rv_core_ibex_icache_invalidate 3600.197s 0.000us 0 3 0.00
chip_sw_rv_core_ibex_fault_dump 3 3 100.00
chip_sw_rstmgr_cpu_info 899.330s 6221.429us 3 3 100.00
chip_sw_rv_core_ibex_double_fault 3 3 100.00
chip_sw_rstmgr_cpu_info 899.330s 6221.429us 3 3 100.00
chip_sw_rv_core_ibex_mcounteren_writable 3 3 100.00
chip_sw_rv_core_ibex_mcounteren_writable 336.310s 2575.580us 3 3 100.00
chip_jtag_csr_rw 2 3 66.67
chip_jtag_csr_rw 2839.500s 22741.799us 2 3 66.67
chip_jtag_mem_access 3 3 100.00
chip_jtag_mem_access 2602.300s 23578.520us 3 3 100.00
chip_rv_dm_ndm_reset_req 3 3 100.00
chip_rv_dm_ndm_reset_req 576.670s 5196.957us 3 3 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 3 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 455.150s 2869.122us 0 3 0.00
chip_rv_dm_access_after_wakeup 0 3 0.00
chip_sw_rv_dm_access_after_wakeup 345.960s 2951.499us 0 3 0.00
chip_sw_rv_dm_jtag_tap_sel 5 5 100.00
chip_tap_straps_rma 624.490s 5140.658us 5 5 100.00
chip_rv_dm_lc_disabled 0 3 0.00
chip_rv_dm_lc_disabled 240.290s 5217.181us 0 3 0.00
chip_sw_plic_all_irqs 9 9 100.00
chip_plic_all_irqs_0 992.520s 4517.779us 3 3 100.00
chip_plic_all_irqs_10 572.420s 3846.236us 3 3 100.00
chip_plic_all_irqs_20 724.650s 4222.890us 3 3 100.00
chip_sw_plic_sw_irq 3 3 100.00
chip_sw_plic_sw_irq 313.280s 2641.847us 3 3 100.00
chip_sw_timer 3 3 100.00
chip_sw_rv_timer_irq 364.710s 2974.373us 3 3 100.00
chip_sw_spi_device_flash_mode 2 3 66.67
rom_e2e_smoke 5140.290s 15396.813us 2 3 66.67
chip_sw_spi_device_pass_through 3 3 100.00
chip_sw_spi_device_pass_through 490.910s 3796.285us 3 3 100.00
chip_sw_spi_device_pass_through_collision 0 3 0.00
chip_sw_spi_device_pass_through_collision 446.130s 3119.379us 0 3 0.00
chip_sw_spi_device_tpm 3 3 100.00
chip_sw_spi_device_tpm 504.090s 3672.384us 3 3 100.00
chip_sw_spi_host_tx_rx 3 3 100.00
chip_sw_spi_host_tx_rx 442.980s 3468.277us 3 3 100.00
chip_sw_sram_scrambled_access 6 6 100.00
chip_sw_sram_ctrl_scrambled_access 705.140s 4539.930us 3 3 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 750.130s 5139.495us 3 3 100.00
chip_sw_sleep_sram_ret_contents 0 6 0.00
chip_sw_sleep_sram_ret_contents_no_scramble 304.800s 3094.933us 0 3 0.00
chip_sw_sleep_sram_ret_contents_scramble 354.250s 2897.833us 0 3 0.00
chip_sw_sram_execution 3 3 100.00
chip_sw_sram_ctrl_execution_main 1207.770s 7973.684us 3 3 100.00
chip_sw_sram_lc_escalation 95 106 89.62
chip_sw_all_escalation_resets 902.200s 5446.073us 89 100 89.00
chip_sw_data_integrity_escalation 917.780s 5901.679us 6 6 100.00
chip_sw_sysrst_ctrl_reset 6 6 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1227.020s 6845.607us 3 3 100.00
chip_sw_sysrst_ctrl_reset 1906.570s 22860.498us 3 3 100.00
chip_sw_sysrst_ctrl_inputs 3 3 100.00
chip_sw_sysrst_ctrl_inputs 405.290s 2935.025us 3 3 100.00
chip_sw_sysrst_ctrl_outputs 3 3 100.00
chip_sw_sysrst_ctrl_outputs 500.470s 3362.049us 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 3 3 100.00
chip_sw_sysrst_ctrl_in_irq 660.060s 4586.029us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 3 3 100.00
chip_sw_sysrst_ctrl_reset 1906.570s 22860.498us 3 3 100.00
chip_sw_sysrst_ctrl_sleep_reset 3 3 100.00
chip_sw_sysrst_ctrl_reset 1906.570s 22860.498us 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3614.230s 20447.097us 3 3 100.00
chip_sw_sysrst_ctrl_flash_wp_l 3 3 100.00
chip_sw_sysrst_ctrl_ec_rst_l 3614.230s 20447.097us 3 3 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 3 6 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 647.080s 6014.538us 3 3 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 3600.194s 0.000us 0 3 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 297.610s 3126.991us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 323.320s 3090.922us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 476.850s 3761.654us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 695.450s 3652.303us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 2069.640s 8197.533us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 8643.960s 31142.860us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 2653.050s 12014.340us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 305.060s 2968.787us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 3 3 100.00
chip_sw_aes_masking_off 477.670s 2731.126us 3 3 100.00
chip_sw_rv_core_ibex_lockstep_glitch 2 3 66.67
chip_sw_rv_core_ibex_lockstep_glitch 225.940s 1977.009us 2 3 66.67
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 0 1 0.00
chip_sw_coremark 18000.188s 0.000us 0 1 0.00
chip_sw_power_max_load 3 3 100.00
chip_sw_power_virus 2088.980s 6646.638us 3 3 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 132.090s 2010.886us 0 1 0.00
rom_e2e_jtag_debug_dev 139.270s 2172.238us 0 1 0.00
rom_e2e_jtag_debug_rma 124.420s 1868.261us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 145.350s 2116.335us 0 1 0.00
rom_e2e_jtag_inject_dev 146.180s 2311.672us 0 1 0.00
rom_e2e_jtag_inject_rma 142.430s 2052.124us 0 1 0.00
rom_e2e_self_hash 0 3 0.00
rom_e2e_self_hash 117.950s 0.000us 0 3 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 3 0.00
chip_sw_clkmgr_jitter_frequency 542.220s 3563.128us 0 3 0.00
chip_sw_edn_boot_mode 3 3 100.00
chip_sw_edn_boot_mode 629.340s 2803.735us 3 3 100.00
chip_sw_edn_auto_mode 3 3 100.00
chip_sw_edn_auto_mode 1799.700s 5850.711us 3 3 100.00
chip_sw_edn_sw_mode 3 3 100.00
chip_sw_edn_sw_mode 2654.650s 10476.807us 3 3 100.00
chip_sw_edn_kat 3 3 100.00
chip_sw_edn_kat 470.360s 2209.424us 3 3 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 331.670s 2630.129us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 3 3 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 670.670s 6797.348us 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 3 3 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 702.360s 5183.158us 3 3 100.00
chip_sw_all_resets 3 3 100.00
chip_sw_pwrmgr_all_reset_reqs 2040.270s 10646.171us 3 3 100.00
chip_sw_rom_ctrl_digests 3 3 100.00
chip_sw_kmac_app_rom 752.070s 7031.508us 3 3 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 132.090s 2010.886us 0 1 0.00
rom_e2e_jtag_debug_dev 139.270s 2172.238us 0 1 0.00
rom_e2e_jtag_debug_rma 124.420s 1868.261us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 2 3 66.67
chip_sw_rv_dm_access_after_escalation_reset 729.310s 4379.746us 2 3 66.67
chip_sw_plic_alerts 89 100 89.00
chip_sw_all_escalation_resets 902.200s 5446.073us 89 100 89.00
tick_configuration 0 3 0.00
chip_sw_rv_timer_systick_test 7200.195s 0.000us 0 3 0.00
counter_wrap 0 3 0.00
chip_sw_rv_timer_systick_test 7200.195s 0.000us 0 3 0.00
chip_sw_spi_device_output_when_disabled_or_sleeping 0 3 0.00
chip_sw_spi_device_pinmux_sleep_retention 340.570s 2370.247us 0 3 0.00
chip_sw_uart_watermarks 5 5 100.00
chip_sw_uart_tx_rx 766.090s 4188.499us 5 5 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3783.060s 19276.200us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 22 13.64
chip_sw_rstmgr_rst_cnsty_escalation 74.000s 10.260us 0 3 0.00
chip_sw_otp_ctrl_rot_auth_config 131.730s 1749.295us 0 1 0.00
chip_sw_otp_ctrl_descrambling 410.770s 2868.373us 3 3 100.00
chip_sw_pwrmgr_lowpower_cancel 348.270s 3121.905us 0 3 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 14.603s 0.000us 0 3 0.00
ate_bootstrap_flash_erase 1306.040s 10010.360us 0 3 0.00
ate_bootstrap_one_frame 10800.852s 0.000us 0 3 0.00
ate_bootstrap_disjoint 10800.202s 0.000us 0 3 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 90 test runs
chip_sw_alert_handler_lpg_sleep_mode_alerts 67404956977918841492489493372319083354866472704618852184063658279160194673397 373
UVM_INFO @ 3063.761766 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 106240030009826435094440975769800144941808608298486044593345541283640241062852 378
UVM_INFO @ 2447.705644 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 92363452082194214982180866550724178197282377560262589374420215752012313881072 378
UVM_INFO @ 2568.762500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 19797062316560264810216064845274877231772357809206639094192397292736457675356 378
UVM_INFO @ 2924.976035 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 26875886298948700992033852821669592302393958011705534515977080620185136222665 378
UVM_INFO @ 2752.007012 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 56676595516287234479928787160796899521481859996693571706601171857210390704899 373
UVM_INFO @ 2306.164851 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 4808033102693074469947776904396296157959390962728060632535064176741825776879 373
UVM_INFO @ 2863.549477 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 16125754781767307024693296804433002858376124134019230506808350808522920424590 373
UVM_INFO @ 2920.488632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 89063332531111319698988744364048521877464137830319685500860469674544463480748 373
UVM_INFO @ 2832.639218 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 28969419542903534662047486678921822907761500730606914496378847894984414898847 373
UVM_INFO @ 2695.914952 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 114789115204657896179510688301305227975094267179472507794195533640088279706393 378
UVM_INFO @ 2224.892694 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 101668977540366715571565729415663681069259738533881600314078152296664723517382 378
UVM_INFO @ 2507.164138 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 43750771432041783979919884958329924408365740086306613924000626449665819834376 378
UVM_INFO @ 2391.188776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 77055865953161364652967951839112294620061241995444012320896487961047835593242 378
UVM_INFO @ 2491.868028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 98462643328227087049040413338786711805492804088182297548178538567275606117377 378
UVM_INFO @ 2771.672670 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 107493996112073520373159098621382227576189547084632585867186840984283736841837 378
UVM_INFO @ 3115.247860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 36921964304623291068058823666183494055665930241669973251441710205832539444690 378
UVM_INFO @ 2625.748155 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 16668971753939868438589852748104205269610915206191649742369974288420526978395 378
UVM_INFO @ 3034.579060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 46580130213187843843616335470535744536563245723642158954104332778826023170194 378
UVM_INFO @ 3096.432000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 45738258349809041798101605633866669356448661102240848078904699048208833387455 378
UVM_INFO @ 2539.139700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 95147744706766310005058119091457574792953853743279408432719678622987306675569 378
UVM_INFO @ 2745.124924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 27741364826467506943336117757209840269092538826425441715371017352723187767226 378
UVM_INFO @ 3067.340419 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 74717797484589781509605593118480940452872573946066187862490321324546428185034 378
UVM_INFO @ 2558.086872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 7730914278463972958924030340082228193857727676275414620375141789177962136839 378
UVM_INFO @ 3031.106780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 96455191021064773013435332792350424078206366401853644559714171067336456361042 378
UVM_INFO @ 2614.240444 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 42559517647295534697472260718724323917606636422008627025214426885532023772349 378
UVM_INFO @ 3013.222100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 20771377045142394489379795895397201460748971375980142270132914472508364462825 378
UVM_INFO @ 2683.004080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 38985641201150962997377615930365481206402326631921147943828850015293013079114 378
UVM_INFO @ 2919.969778 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 59579414777444002009491185445439135281942307707594802331393000273546711623442 378
UVM_INFO @ 2493.763013 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 88306174633916575591261498835938570656046226158622146313539211167593988149602 378
UVM_INFO @ 2668.003604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 56492580877605722474106599331805371350765166785509752217360761249880352315401 378
UVM_INFO @ 2276.883033 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 46311739741556290054792196657442641718032180199420487220916016472221857316416 378
UVM_INFO @ 2197.630392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 3448331667000880589248286590571843761585196074606898435481583436742980844102 378
UVM_INFO @ 2132.867072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 109136609171137782622213041756646300187946684965304589100676921227693668715511 378
UVM_INFO @ 2437.919414 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 109579651370236999107844612667615780419647430824415697869995354933260733616415 378
UVM_INFO @ 2805.305093 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 39411893232056879495563828644670689519119757341069997075664914657407487547128 378
UVM_INFO @ 2550.757403 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 70036373732326406386347283442664647346409567319202020246400136138675333352233 378
UVM_INFO @ 3065.680836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 6567369844906432041976421546850437444741013732882815440674594454039857920382 378
UVM_INFO @ 2787.960080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 55037943275173947998788516989243096756630585485596762596549444970434077479680 378
UVM_INFO @ 2520.883037 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 54310506267073062032390435072003036678675372805858944160220123004802625160641 378
UVM_INFO @ 2840.030170 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 42640624962912420704377629909059686237811476859850373763552136472885865272434 373
UVM_INFO @ 2469.637505 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 7789154252443318796375939053568778477201007998542300098203142376932089917938 378
UVM_INFO @ 2425.471138 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 42127662629367357790222464249236982653778865446630246916726884224045783015505 378
UVM_INFO @ 2650.287810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 58481228348350926454121314432631717257388199426475774656078110646800998953611 373
UVM_INFO @ 2659.481660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 33592052146553611513516883578061854529606278865824204660936886893343712108465 373
UVM_INFO @ 2538.217125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 102619828711060231778834111787695728300116574581319730118315282895239442488476 373
UVM_INFO @ 2346.470808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 35567484926377527299320407023287403207966967418979389256710854500607323342011 373
UVM_INFO @ 2383.141092 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 13078673427195370275635399952404472556366664565361711847750629182391120933419 373
UVM_INFO @ 2571.187240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 46551572010532025407048950364953815433675626334102919875652877080437246478019 373
UVM_INFO @ 3101.809748 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 86762030291934930800826712061961018763090343711255479964078145295578454745428 373
UVM_INFO @ 2877.382842 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62141199339353730882959836485029521044170536402183420364726043514708241653026 373
UVM_INFO @ 2241.703725 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 94786908343698002588831019096451147384586286739654302259923455945521492952424 373
UVM_INFO @ 2489.379464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 109828578573318877181300461109447340135943035801090047270879621392820905743462 373
UVM_INFO @ 2198.191180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 38608163533352791555448049318276897706030328373220917222644063770275492244434 373
UVM_INFO @ 2780.043696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 63716631697838300121998213477749514110478235274504192207096097216149256330496 373
UVM_INFO @ 2835.301745 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 15463984790529667135208332427979504738222305562849391905293085035965805042726 373
UVM_INFO @ 2572.095544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 51654348201867349640360905043320543319460770550515254208328426474897073766575 373
UVM_INFO @ 2492.610000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 69859679596669483184241497973492619958119738840037738791782561666861258164493 373
UVM_INFO @ 2453.733690 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 10828139075358798039743952440577873023132977524442376830413126724452424452758 373
UVM_INFO @ 2186.553071 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 104509289480756847465126853833496277948896809772969946444197743900762272608902 373
UVM_INFO @ 2904.364714 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 104481740706143323303311402032141822040514817354474663395025490929508552665278 373
UVM_INFO @ 2892.600109 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 41486798037629307607107258163861690420262373839097368293035491764865109500521 373
UVM_INFO @ 2655.488008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 62951616833970341635180592397048137527317802872940157760404699810903815073361 373
UVM_INFO @ 2745.259531 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 35165132869296857401858696422654760883228680778035802535891440457613206989931 373
UVM_INFO @ 2172.540260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 95959763946453116322077780905076536103286669032930778132063823431637865262304 373
UVM_INFO @ 2742.838316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 39339473593159407064665134008537810239959265016969813733395608336901027530190 373
UVM_INFO @ 3003.656355 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 69025096794288760209559967785484744869887666473612328054533624688912052507804 373
UVM_INFO @ 2654.437352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 55343504898094986226828761991065085396490316282270957710992309301785509957149 373
UVM_INFO @ 2676.089660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 91544595337988417278857790484678045644158845279478686079277416119023175670326 373
UVM_INFO @ 2224.916700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 26482788620765976373620196558486982501413704622762227944164122778957480868188 373
UVM_INFO @ 2435.161340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 41712242770147827758003477574121809914319068621414631509835786008071128709057 373
UVM_INFO @ 3028.740680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 82913197635089137518628385794156900165322226798028266273806963177794773721087 373
UVM_INFO @ 2760.774040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 89269640354167824958465308155229819168594170182543711507795558743438515499597 373
UVM_INFO @ 2684.853680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 75926781022322987502715321638795045432624483096394603690283468074349982652109 373
UVM_INFO @ 2256.551130 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 61079337444291860340352415570202349807679330413612118380521574963443865879396 373
UVM_INFO @ 2930.132530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 33543296113076393186206862366767685525294850545512474946209836243953145987648 373
UVM_INFO @ 2477.316232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 97831690993262513547054148136933910296497435995744879708211820113034058936117 373
UVM_INFO @ 2331.400384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 114193622272128996098696701849032583501153583459541287009778630072672488603777 373
UVM_INFO @ 2609.938691 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 14329419055463454442729021079662593603639712252181697415181204261974814942073 373
UVM_INFO @ 2264.590764 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 15020450450138189581501502548252706912422943788070325376620282346209849704791 373
UVM_INFO @ 3131.007975 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 74614903937518544891289893867387845162682087690149047767962742908887132913099 373
UVM_INFO @ 2985.885147 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 22655894955743292555822031542808940232528577988916170286304968294577165358753 373
UVM_INFO @ 2479.013220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 60944448952072676297888226187273490927280054357499985395002239941249364937582 373
UVM_INFO @ 2347.805140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 67865523725617289552106908807576346786990263822453547221250369227485365715309 373
UVM_INFO @ 2759.464735 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 23188920107947027482813243797834511764449128728025429952256533315789293144150 373
UVM_INFO @ 2516.081384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 75743874820708750279983775912649753623474141551828979632840269376780028244053 373
UVM_INFO @ 2653.478504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 75529115332968951771558837616040654220933666223939864107552986384340938113074 373
UVM_INFO @ 2231.770972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 96622888492688899956041856423375038161720204529700754617977123226342945444082 373
UVM_INFO @ 2323.346330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 1226329681823734807039464558248287574555631465463928695189152719019788007014 373
UVM_INFO @ 2949.542180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_alerts 74119722727901689877763998181218785733027354705185629210670733845158144310292 373
UVM_INFO @ 2582.336945 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:254) scoreboard [scoreboard] alert fatal has unexpected signal int error 46 test runs
chip_sw_sleep_pin_wake 96405254909829381660492887433133031333909557256196270385147604381908579185071 382
UVM_INFO @ 3347.811768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_retention 9967057335256980071781708909655888939159768542142014858838164110179430165725 379
UVM_INFO @ 2989.587684 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 63860282267002871707271220239746370312509801766837276708036718597160225432192 374
UVM_INFO @ 2999.120788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 88311105545184287339213916735267634852207354391460038549556992822310936729725 397
UVM_INFO @ 7743.715632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 8235011773040922087690354244757457036166790883891057481788553095429505925385 382
UVM_INFO @ 4276.484424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 58905610331114490463002298338768218145864514382784711035244421139585460543131 388
UVM_INFO @ 4763.075523 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 52472182390598067495654669448787074993600789622606730119418907079184409802373 384
UVM_INFO @ 3757.540146 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 104977853211531891135900896062401863624273168499215921456294389993895822499045 377
UVM_INFO @ 3094.932948 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 18205215896145698265968950037829635056257195178785556956844841725655170260902 381
UVM_INFO @ 2729.212416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 46504758957332076486578769711965074021913554315225253328615443469630019450569 372
UVM_INFO @ 2193.437544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 40030621255160679732683603841215971551038419554942747616765780543139417042559 407
UVM_INFO @ 4661.745760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 87620498098651180458973591008990365752122332498568085001771052239213281848755 374
UVM_INFO @ 2886.044388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 38830178300986152428223779626344253542529093398200263763067588153484109080972 372
UVM_INFO @ 3121.905244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 40022629349106893979195401520191785462513802376166147921011468000600213685300 373
UVM_INFO @ 3190.922928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 50659851574147983876122524524143806233526206922721937633435995610405560167732 390
UVM_INFO @ 3181.956956 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_wake 54314683931246507049922697627306959605860899167824848194795664323293148061265 382
UVM_INFO @ 2912.445072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_retention 98358285691209284519610018992951866638482640895512133772661671590152862141317 379
UVM_INFO @ 2683.238220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 97372981636854089418205875210288645954990696185646625002951347334209912676096 374
UVM_INFO @ 2664.909892 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 42222506615652139312319840997074998446988213425923301071986533035214757285370 392
UVM_INFO @ 7751.266056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 87232475794706517033482932913574119477587556665947741429379749302278858395959 377
UVM_INFO @ 3496.220706 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 99324866223984014566752664009041672214665136598787235272622836445704650628970 388
UVM_INFO @ 4849.574604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 21596364358578908914286141506508510863362556124718566567345736695048393188960 379
UVM_INFO @ 3707.708760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 24931616083390408335663756520579634770712707658693954381342137108694422099254 377
UVM_INFO @ 3038.711042 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 46667872761933565963547675774538018027939459269470198658851150163868793905745 381
UVM_INFO @ 2897.832736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 7307690471412308108410011461757315142975355092423964627966771411008889077562 372
UVM_INFO @ 2861.852816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 89907284154652558247541336882787489507123485619234210858085565995174978160798 407
UVM_INFO @ 4194.329512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 12624707534631108554419575449106743112585096051049088922168045252957063745148 374
UVM_INFO @ 2685.970376 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 66248807500574973872818048758623659861090134949776864898359251676520155039547 372
UVM_INFO @ 3063.748666 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 7108423623013429769142536625643007621436420344104032784419189115518517835089 373
UVM_INFO @ 2527.892672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 459664243291409505058006560913546114793403613304215169957445143150662325779 390
UVM_INFO @ 2935.266336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_wake 97277041114626165309997610982432363887551595808717805028877276819120969543038 382
UVM_INFO @ 3531.743160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_pin_retention 115285441573548113154636857887482630594503967287665119291862774662175678115095 379
UVM_INFO @ 2529.178568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_spi_device_pinmux_sleep_retention 107634607203512811635524717107549718125781088786322930708070926846164625040910 379
UVM_INFO @ 2370.246984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_reset_reqs 43459917880110574187811769119254499816148708370758532537791699011151316588528 397
UVM_INFO @ 6400.099632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 59052223033050694407566195554172520042757483906416002815018337068058913741517 382
UVM_INFO @ 3909.894096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_por_reset 17735799471393272805559459235496642218678609471573055716391497595968298187925 388
UVM_INFO @ 4931.773440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 39542328531220415956988087767486901945611522037454128735583747005220542490484 384
UVM_INFO @ 3358.011240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_no_scramble 38334067973035348404654360461934343773683875352329426068530295285093012805019 377
UVM_INFO @ 2932.194564 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sleep_sram_ret_contents_scramble 18366907805951103311588183206863082975961385605487868039510782523221882236690 381
UVM_INFO @ 2980.157754 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 83429366813328135668556663495029203433429832068968076296410664090615420820660 372
UVM_INFO @ 3119.161080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_sleep_frequency 81544546961673326761154294337786110924751255168465984721004880609350235480681 407
UVM_INFO @ 4685.140792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_normal_sleep_all_wake_ups 103995241823732792533688926582466514261578983520489714525695822334357216110771 374
UVM_INFO @ 3332.832678 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_lowpower_cancel 59567727299390042580665199425543572988915155449941346064267509732558415431816 372
UVM_INFO @ 3257.591544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_all_wake_ups 33650967374516491509870340537447465039162796985206475948258877371040759208980 373
UVM_INFO @ 2736.619840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rv_dm_access_after_wakeup 65044369083648080924932516922413686770435033366197785815894580655790189724086 390
UVM_INFO @ 2951.498548 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_power_sleep_load 19308552041407683204040244602601902835300368039441591397551491648255515900202 387
UVM_INFO @ 3204.889394 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 37 test runs
chip_csr_aliasing 60581356096926680278156407451916616938366087591245797441715081747061065059509 None
chip_sw_uart_tx_rx_bootstrap 108912309895430429624890392277249011704590048752417022413384160472725477291362 None
chip_sw_exit_test_unlocked_bootstrap 103893330780824063171083820480457042065226548749717346252157634109849459616240 None
chip_sw_lc_walkthrough_testunlocks 49060135497655390764857691944431567640106530325433103905697304111980624664800 None
chip_sw_rv_timer_systick_test 100961969665565737113702072581990207189706513966101912036338910740315382498910 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 28579536850740809000884586199959292705532805517757799184094145699846342726956 None
chip_sw_alert_handler_reverse_ping_in_deep_sleep 23134153594517578111419405756148136645098511897376959562579587179231737379146 None
chip_sw_keymgr_dpe_sideload_otbn 37570808447445230357781463299284418910660949771018483579700413846885762416691 None
chip_sw_coremark 19507603496632210760441812263272621027385009568086891297707971148496258866035 None
chip_tl_errors 50080605640592765378332184806431818036210536327149150098292940171282339519829 None
chip_sw_rv_core_ibex_icache_invalidate 32553727122714409419747004041033616317296332340997113569901178351931254570394 None
ate_bootstrap_one_frame 91721789811427357595679850362402815760923615625789607296379190269847565001708 None
ate_bootstrap_disjoint 73694396924911462869334605404133766520185199021160559319416427267498676776486 None
chip_sw_uart_tx_rx_bootstrap 85086934938856799669033142412718656388609506949165170113807479524596530669078 None
chip_sw_exit_test_unlocked_bootstrap 25848459849709424763871228019270066518018733303088058160116675011161717707564 None
chip_sw_rv_timer_systick_test 103499938693328783578847898785482738606572999062389430315655405576713082220404 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 83265436589296487143242562252848569312078054578388326098022849622564454785998 None
chip_sw_hmac_multistream 83275214304570983546870476676539053568791102095688434060078303163307637954625 None
chip_sw_keymgr_dpe_sideload_otbn 49069664721327354683057888868156902506014779759758890757792221484601526268697 None
chip_sw_rv_core_ibex_icache_invalidate 68342353734714887766999985075045445631335476680795873308464128798669489147378 None
ate_bootstrap_one_frame 35906381211490826234859200016521538804427375857085674343405237058903047805513 None
ate_bootstrap_disjoint 83292271188530966605565162742659736789380053238197782387493209554755656989657 None
chip_sw_uart_tx_rx_bootstrap 14733518354270500897432454333821762416727244052572047256175033417490510334552 None
chip_sw_exit_test_unlocked_bootstrap 32678217148102514500069254745787768443919649559044503000493220710446689698436 None
chip_sw_lc_walkthrough_testunlocks 83390169971612109821268280668800550167741489155532278727796297893322652174049 None
chip_sw_rv_timer_systick_test 53937435875040088723997057916777218242693072129587393170162667455033990138002 None
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 68024943018081088766511631883919669566551567029242876240124643838899089758184 None
chip_sw_alert_handler_reverse_ping_in_deep_sleep 87352722428734775776756476896066046303237099900067762479498193899326552651031 None
chip_sw_keymgr_dpe_sideload_otbn 75610193825850243178687541811703790756095007508977151735151379761215305725416 None
chip_sw_rv_core_ibex_icache_invalidate 56774921162951285480609211369080101080750142510195998052143632391266323190393 None
ate_bootstrap_one_frame 9906937735872314161209453527311854716681496305578498483398229708187212109094 None
ate_bootstrap_disjoint 65395872980584259442819740485399902521930410580225393990688470523484641953001 None
chip_same_csr_outstanding 41397597429614818889590336347857048593477424252322733363702236043985863629462 None
chip_tl_errors 44475455122530370116116279137394522086704378314309833361178617253561441292048 None
chip_tl_errors 11680787162472987087506054005699052003926362497742046656617845538193907076278 None
chip_tl_errors 69244144524347414506465709029711052228788210126542021873203086126533064916201 None
chip_tl_errors 32277631876974792629193675167785231482170223641106881138085997248294031113356 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 8 test runs
chip_sw_rstmgr_alert_info 43017437551206825351283262117306279588759135273806174647065071964865039366326 949
UVM_INFO @ 10451.263852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_pings 43764133321734518370102569718545350163533632895607524095797398088677833670615 373
UVM_INFO @ 2684.301956 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 80557012044896629402681136394963942384105077043912258069104765173569058492557 437
UVM_INFO @ 3381.270960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_reverse_ping_in_deep_sleep 73328181543975028533720679866531901297533352714506934918600506100861288676193 377
UVM_INFO @ 44889.250938 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_pings 19917529160397756732130120770989352525691657720493335830165603960035664660529 379
UVM_INFO @ 2831.994317 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 60771455603873668551044548727894811719718911339107344186914735981923270379869 494
UVM_INFO @ 2734.602696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_lpg_sleep_mode_pings 30402250575540034912806390380646578941282749921198147678646457688428621385856 378
UVM_INFO @ 2448.890424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_alert_handler_entropy 73497641083656181070113154316233830441348778986151750198517842665295679132010 494
UVM_INFO @ 2788.278612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access 7 test runs
chip_sw_otp_ctrl_rot_auth_config 41610686962472646212688781619232486177324448148554835222026126311309034634122 379
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 22170623275286445451315833562198210430090024722133610925121057832423438100335 403
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 72118283151141388438434652909144806041430293516902568993649963363316340674926 379
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 85999400953250803647549573459002385038487082852223012335923342548083761009114 379
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 11668861439458990873386720316569376407509344915601908791408912741888195641756 381
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 74556879340965382607684404558981244975095243167127867455770472628616697900870 403
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 5861403252454456183218269641205645153490793305890603423663972542083792310617 403
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 7 test runs
chip_sw_lc_walkthrough_dev 102163719259596090175860267470735006848862765456557812234463753949862791591566 433
UVM_INFO @ 16403.989914 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 56744714961391007488050859201035438517506898105016420986016568514953363881555 433
UVM_INFO @ 21397.933352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 107862276621288201002800920899867881091407877181148151436516113098082550646724 405
UVM_INFO @ 11546.781208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 29661770838194252216737258947283679335480801036717218827855128738471826532320 438
UVM_INFO @ 18950.269264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_dev 89062611495023185937983543864915741283692836442763655681315097023357277126824 438
UVM_INFO @ 17343.036574 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 3127280222210379167052845791206448620484061046675981299742898407530149854716 438
UVM_INFO @ 21072.452750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 106727527797781816610525666349564998923731064256297932824258964445315268220138 410
UVM_INFO @ 15258.328604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 6 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 112633542482927928293481677225663702904623302505021753401321674377256188574281 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 114139665036300094333875495734712842941454154441627816909972438236426375034120 None
Another command (pid=221632) is running. Waiting for it to complete on the server (server_pid=195193)...
Another command (pid=223390) is running. Waiting for it to complete on the server (server_pid=195193)...
Another command (pid=197745) is running. Waiting for it to complete on the server (server_pid=195193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 61099992223811490703640131581049178092245917132643222148331712735116671570740 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 113781889824673404996790177614415042034076229404304959825787208674875519356896 None
Another command (pid=225537) is running. Waiting for it to complete on the server (server_pid=195193)...
Another command (pid=235644) is running. Waiting for it to complete on the server (server_pid=195193)...
Another command (pid=248471) is running. Waiting for it to complete on the server (server_pid=195193)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
chip_sw_pwrmgr_sleep_wake_5_bug 50387473164061124556889063201259401921639130169596077992622796359674922278479 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 75303213743439850828640303450395122082913631743129655564012802955440411446296 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_ERROR @ * us: (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal triggered unexpectedly 4 test runs
chip_same_csr_outstanding 16075721922732451087631254488173645091354559221420695877470702389398588876592 287
UVM_INFO @ 7398.323912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 25309622702471325134419554060095241132990459536707712490064272336437606466175 382
UVM_INFO @ 2896.342884 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 29029557444052624433336366943923116130064021950319515130911883495517278194648 382
UVM_INFO @ 3193.281144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 19768838929350516759212030080790876298140178449148852251648827899654182420186 382
UVM_INFO @ 2431.948554 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:1072)] Unexpected fault 4 test runs
chip_sw_all_escalation_resets 22366189591345169149475082956432256080962409990943205990241686777264889127464 375
UVM_INFO @ 3081.066912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 78198126180422312581759812076467558215259927016265405895287153356977519798466 375
UVM_INFO @ 3053.539346 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 82045429273368643263132629936068512419936233937549167055879896560348655371283 375
UVM_INFO @ 3073.310050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 38519435998145312416833711051441160647378396496218923983343797614233473493695 375
UVM_INFO @ 2965.203480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 3 test runs
chip_sw_rstmgr_rst_cnsty_escalation 108274397257437172562007783796872497048173259951828236948966336329626495321400 365
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 44731563397276881601377126952437084047452146285907046160950586407287575871067 365
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_rst_cnsty_escalation 98863454986262019815246070443122551326577347857877721101637754306849733504759 365
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rram_rma_unlocked_vseq.sv:162) [chip_sw_rram_rma_unlocked_vseq] wait timeout occurred! 3 test runs
chip_sw_rram_rma_unlocked 59664132497903320321776684012964999927711632393536062074275756146121644118866 337
UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rram_rma_unlocked 10611698785409776228098266998949206253786269450798615881488028567957661305652 337
UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rram_rma_unlocked 7762001851096266313254389791455598719622632924568857759355801202480124487887 337
UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 3 test runs
chip_sw_otp_ctrl_lc_signals_rma 53290158296528952146899544716010757166978903250790386100143723040299833712127 404
UVM_INFO @ 6994.201416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 73899770374976001445567465063808209632470628299363336226167291579551092509028 404
UVM_INFO @ 5111.194198 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_otp_ctrl_lc_signals_rma 97409391134837210411839428266988496564928812119192785940678608295702352433245 404
UVM_INFO @ 6270.660320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 3 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 45032867137780105748945882295885438685567452369338194009701266443050130289611 377
UVM_ERROR @ 2551.144800 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2551.144800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_power_glitch_reset 18826887335130327057709262368711283163984054003784133792724022703244287359851 377
UVM_ERROR @ 2271.071320 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2271.071320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_sleep_power_glitch_reset 72579449515094284104398443885427162635876499129756627945868110562444446222837 377
UVM_ERROR @ 2749.119042 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2749.119042 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_test_status_if.sv:65) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] SW test status must not change after reaching the pass or fail state. 3 test runs
chip_sw_clkmgr_reset_frequency 12082922737616035215855506275326914542107361689059495571205608011860874152335 400
UVM_INFO @ 11022.049460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_reset_frequency 80647657056823623444687721047633882902512388295118269412823976034368326510552 400
UVM_INFO @ 11291.600800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_reset_frequency 29987045088934153371837039555397963966442677662265767824002265262647198188858 400
UVM_INFO @ 11597.939944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_clkmgr_jitter_frequency 38087163164752819904316385102459088807609901529613405363741747101610185532721 407
UVM_INFO @ 3542.269018 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 37465441957570130517183685278718082343392831389227815153057174902434464402540 407
UVM_INFO @ 3563.128480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_clkmgr_jitter_frequency 9752368626157942839641074010078135180458102349888160861383657829740019592426 407
UVM_INFO @ 3096.910499 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 3 test runs
chip_sw_ast_clk_rst_inputs 95430201983337760574566713882707369519495352891973084547660822490703040544956 391
UVM_INFO @ 7888.441476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 81573528559232310366537043254429928053954104669717629040955473735217094487149 391
UVM_INFO @ 14002.928817 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_ast_clk_rst_inputs 45897466574459246179759301748712569516142873097702150511354050326275987343145 391
UVM_INFO @ 14714.156278 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 3 test runs
ate_bootstrap_flash_erase 49924780165227502269504958246656660536252126647207223250939516712035016692699 339
UVM_INFO @ 10010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ate_bootstrap_flash_erase 64332624841284424370275740708017510923578116409374912282148780027679646085413 339
UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ate_bootstrap_flash_erase 34675834340675763492189890681334179211062691120044078131993886909814124733011 339
UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:604) [debugger] Check failed pc == exp_addr (* [*] vs * [*]) 3 test runs
rom_e2e_jtag_debug_test_unlocked0 52273902769491741147731325344768592267388753448657046441092659890413402423889 359
UVM_INFO @ 2010.885500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_jtag_debug_dev 109135635540798387148909660164380829649935576119811839021916497363868819051365 359
UVM_INFO @ 2172.237500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_jtag_debug_rma 16169235379212666795498024293264188236210715821661028123526609457945233588093 359
UVM_INFO @ 1868.260500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(pend_req[h2d.a_source].pend == *)' 3 test runs
rom_e2e_smoke 99107910066357020939122733360307813751353289466088171623708758202669765786424 385
UVM_ERROR @ 1870.249458 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 1870.249458 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_shutdown_output 86485976512652629003832099036661684456281330817087997011282294731436671627265 378
UVM_ERROR @ 4938.248083 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 4938.248083 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 89991475193888935581009962969306332027646902114113604702770219397977676414125 410
UVM_ERROR @ 9876.269372 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 9876.269372 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:614)] CHECK-fail: Unexpected mtval: expected *, got * 3 test runs
chip_sw_all_escalation_resets 95701354432556718699097214896189675037366464984874121854861718592397507608974 383
UVM_INFO @ 3422.937660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 33444027569643486041573564856326321938750526396340363324484151393367860494935 383
UVM_INFO @ 2568.240062 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 82369189595303530932368867147332497907073610099345887739517299001086583484365 383
UVM_INFO @ 3481.732192 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 2 test runs
chip_sw_otp_ctrl_escalation 92639581967922188149030661223119705076244568787071902911115632557746201018309 380
UVM_ERROR @ 2630.129028 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2630.129028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_all_escalation_resets 88432092661478578455985020881178679758696546289010820960689194364065085528690 383
UVM_ERROR @ 2581.945044 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2581.945044 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl 2 test runs
chip_sw_lc_ctrl_raw_to_scrap 53910231175940363636694027752852076663712976751240641679286945602511227820590 375
UVM_INFO @ 11109.560660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_rand_to_scrap 42995436472965992589226023592744243915289153486678906930960554727230350101503 375
UVM_INFO @ 9124.892668 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:340) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 115591386875212034103700085624790439212098451458899108190693773192456259682124 429
UVM_INFO @ 12010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_hmac_multistream 32333252796228369655723988196128624051046631122937100894520258225966995844429 442
UVM_INFO @ 12010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_rv_dm_lc_disabled_vseq.sv:154) [chip_rv_dm_lc_disabled_vseq] Check failed rdata == exp_data (* [*] vs * [*]) RV_DM sbaddress* read back check failed, got *, expected * 2 test runs
chip_rv_dm_lc_disabled 6378854625758968525083668391822707475894610480889863144433369941071105340613 293
UVM_INFO @ 2105.644375 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_rv_dm_lc_disabled 39050512300490726016646319862717758761506073169342214999164330649417129731958 315
UVM_INFO @ 5217.180620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:887) virtual_sequencer [chip_sw_lc_raw_unlock_vseq] Cycle timeout (*) for pinmux to connect JTAG to lc_ctrl 2 test runs
rom_raw_unlock 113526816474700037737739513282641589766632417068027470017163455301111089898532 384
UVM_INFO @ 9136.508164 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_raw_unlock 101832973501060740176750061149057987955868893806399378899654871536076235604135 384
UVM_INFO @ 8642.890645 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch 2 test runs
chip_sw_spi_device_pass_through_collision 88822908850974540087328844537859013975915981434974601326484491201039394878181 393
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
chip_sw_spi_device_pass_through_collision 20661659966669504121820092426226803183821105607550057515885104727607970365349 398
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched! 2 test runs
chip_sw_lc_ctrl_transition 44235266861577622034949679873007620282503019347683176461413498305586078179983 369
UVM_INFO @ 26467.759131 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_ctrl_transition 65954519257435182957694484447360158290576836867931146492284886915946805848446 369
UVM_INFO @ 25638.008816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched! 2 test runs
chip_sw_lc_walkthrough_prod 30638732735484292425899745822064251052704443240397855945774205277734088765357 377
UVM_INFO @ 25894.018604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 86798252987997972113043400623201963351342947914849213163634330798204255656155 377
UVM_INFO @ 26249.332913 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 49146734107262128452172497619715319864334605659897746704915199350083558683929 391
UVM_INFO @ 3119.379344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:340)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 79402190775346918085627482063547028121802742315440580259092614314671179966690 371
UVM_INFO @ 2955.366536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rv_jtag_o == '0)' 1 test run
chip_sw_rv_dm_access_after_escalation_reset 69542377830713308046706107323256060460171186815080374883424311137852757212636 387
UVM_ERROR @ 2689.290388 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A
UVM_INFO @ 2689.290388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. 1 test run
chip_sw_rv_core_ibex_lockstep_glitch 49417589063596497730309690200457184901609250019259397341148331159467944948120 386
UVM_INFO @ 1889.402050 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:923) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_testunlocks 67166857547142294543345950710712393235756132091826646799637569838946394459227 368
UVM_INFO @ 26251.568574 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:415)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 109280428888493786230169285188258161938926320780378234105557400676675988214479 371
UVM_INFO @ 3285.307180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_riscv_driver.sv:208) driver [driver] Could not activate RV_DM after * attempts! 1 test run
chip_jtag_csr_rw 48102222393126508308779190099887878002884692259964516160309965288760386590893 5365
UVM_INFO @ 2069.742602 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_if.sv:154) [tb.dut.chip_if] Detected an X on MioPadIoc* (num=30) 1 test run
chip_padctrl_attributes 77912440720238329612143704030393750456580122033123246215052451523919965111711 366
UVM_INFO @ 1697.929969 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:1004) [chip_sw_lc_volatile_raw_unlock_vseq] Check failed (!(transition_ctrl & (* << *))) VOLATILE_RAW_UNLOCK is not expected to be supported by this top-level. Check the SecVolatileRawUnlockEn parameter configuration. 1 test run
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 2356633348765865430383273655361791964656004166436811890033835459291675586565 378
UVM_INFO @ 2145.589116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:400)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 40048080881455269323683012506542047037874898571150524098851160274842588339596 371
UVM_INFO @ 3240.994591 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 78749724571898287330147378670235588851049792038172656509072136377392140601012 300
UVM_INFO @ 2493.033897 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement 1 test run
rom_raw_unlock 115666077248413810162713418065124558739779657980771354895698613956676421569487 398
UVM_INFO @ 22245.556156 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:198) scoreboard [scoreboard] a_source: * & d_source: * mismatch 1 test run
chip_tl_errors 27085321918357497025174877546005402150247977616235422457716777711278761634657 282
UVM_INFO @ 1778.746836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:689) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 1 test run
chip_csr_mem_rw_with_rand_reset 38303475464657376029512599968463388629448353906453953411844887669560884499594 288
TL item was: req: (cip_tl_seq_item@37876) { a_addr: 'h110008a8 a_data: 'hee4a647d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2b a_opcode: 'h0 a_user: 'h24131 d_param: 'h0 d_source: 'h2b d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 1714.644617 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_if.sv:154) [tb.dut.chip_if] Detected an X on MioPadIoc* (num=27) 1 test run
chip_padctrl_attributes 114543468472091163032509867988203835647867439692499615169404130395326580388023 356
UVM_INFO @ 2239.861717 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---