Simulation Results: clkmgr

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.88 %
  • code
  • 98.57 %
  • assert
  • 95.76 %
  • func
  • 87.31 %
  • line
  • 99.07 %
  • branch
  • 98.75 %
  • cond
  • 95.85 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
79.31%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
clkmgr_smoke 1.550s 152.093us 10 10 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.250s 71.846us 1 1 100.00
csr_rw 5 5 100.00
clkmgr_csr_rw 1.080s 17.682us 5 5 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.400s 291.524us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.110s 26.041us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.640s 44.219us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
clkmgr_csr_rw 1.080s 17.682us 5 5 100.00
clkmgr_csr_aliasing 1.110s 26.041us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 10 10 100.00
clkmgr_peri 1.870s 107.440us 10 10 100.00
trans_enables 10 10 100.00
clkmgr_trans 1.610s 104.904us 10 10 100.00
extclk 10 10 100.00
clkmgr_extclk 1.520s 99.587us 10 10 100.00
clk_status 10 10 100.00
clkmgr_clk_status 1.160s 48.559us 10 10 100.00
jitter 10 10 100.00
clkmgr_smoke 1.550s 152.093us 10 10 100.00
frequency 10 10 100.00
clkmgr_frequency 22.530s 2484.474us 10 10 100.00
frequency_timeout 10 10 100.00
clkmgr_frequency_timeout 17.060s 2416.308us 10 10 100.00
frequency_overflow 10 10 100.00
clkmgr_frequency 22.530s 2484.474us 10 10 100.00
stress_all 10 10 100.00
clkmgr_stress_all 51.670s 7288.071us 10 10 100.00
alert_test 10 10 100.00
clkmgr_alert_test 1.680s 179.405us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
clkmgr_tl_errors 5.840s 530.287us 25 25 100.00
tl_d_illegal_access 25 25 100.00
clkmgr_tl_errors 5.840s 530.287us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
clkmgr_csr_hw_reset 1.250s 71.846us 1 1 100.00
clkmgr_csr_rw 1.080s 17.682us 5 5 100.00
clkmgr_csr_aliasing 1.110s 26.041us 1 1 100.00
clkmgr_same_csr_outstanding 2.350s 188.290us 5 5 100.00
tl_d_partial_access 12 12 100.00
clkmgr_csr_hw_reset 1.250s 71.846us 1 1 100.00
clkmgr_csr_rw 1.080s 17.682us 5 5 100.00
clkmgr_csr_aliasing 1.110s 26.041us 1 1 100.00
clkmgr_same_csr_outstanding 2.350s 188.290us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 15 30 50.00
clkmgr_sec_cm 43.170s 10243.115us 0 5 0.00
clkmgr_tl_intg_err 72.450s 10009.875us 15 25 60.00
shadow_reg_update_error 12 20 60.00
clkmgr_shadow_reg_errors 1381.030s 200000.000us 12 20 60.00
shadow_reg_read_clear_staged_value 12 20 60.00
clkmgr_shadow_reg_errors 1381.030s 200000.000us 12 20 60.00
shadow_reg_storage_error 12 20 60.00
clkmgr_shadow_reg_errors 1381.030s 200000.000us 12 20 60.00
shadowed_reset_glitch 12 20 60.00
clkmgr_shadow_reg_errors 1381.030s 200000.000us 12 20 60.00
shadow_reg_update_error_with_csr_rw 14 20 70.00
clkmgr_shadow_reg_errors_with_csr_rw 1416.340s 200000.000us 14 20 70.00
sec_cm_bus_integrity 15 25 60.00
clkmgr_tl_intg_err 72.450s 10009.875us 15 25 60.00
sec_cm_meas_clk_bkgn_chk 10 10 100.00
clkmgr_frequency 22.530s 2484.474us 10 10 100.00
sec_cm_timeout_clk_bkgn_chk 10 10 100.00
clkmgr_frequency_timeout 17.060s 2416.308us 10 10 100.00
sec_cm_meas_config_shadow 12 20 60.00
clkmgr_shadow_reg_errors 1381.030s 200000.000us 12 20 60.00
sec_cm_idle_intersig_mubi 10 10 100.00
clkmgr_idle_intersig_mubi 2.930s 482.154us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
clkmgr_lc_ctrl_intersig_mubi 1.350s 79.326us 10 10 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.430s 84.189us 10 10 100.00
sec_cm_clk_handshake_intersig_mubi 9 10 90.00
clkmgr_clk_handshake_intersig_mubi 1.960s 267.507us 9 10 90.00
sec_cm_div_intersig_mubi 10 10 100.00
clkmgr_div_intersig_mubi 1.540s 131.710us 10 10 100.00
sec_cm_jitter_config_mubi 5 5 100.00
clkmgr_csr_rw 1.080s 17.682us 5 5 100.00
sec_cm_idle_ctr_redun 0 5 0.00
clkmgr_sec_cm 43.170s 10243.115us 0 5 0.00
sec_cm_meas_config_regwen 5 5 100.00
clkmgr_csr_rw 1.080s 17.682us 5 5 100.00
sec_cm_clk_ctrl_config_regwen 5 5 100.00
clkmgr_csr_rw 1.080s 17.682us 5 5 100.00
prim_count_check 0 5 0.00
clkmgr_sec_cm 43.170s 10243.115us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 10 10 100.00
clkmgr_regwen 8.620s 1352.304us 10 10 100.00
stress_all_with_rand_reset 10 10 100.00
clkmgr_stress_all_with_rand_reset 158.770s 38108.512us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1087) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 12 test runs
clkmgr_sec_cm 33189913073170000069339227304347875172131378995715908910027950953583326094962 87
UVM_INFO @ 10010547705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 18280838053273143947813845693075694801822550916245619077547222712783315996440 234
UVM_INFO @ 10361265262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 91776131245023273091180739397702951715569681128144711263036460399203599824596 136
UVM_INFO @ 10243114504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 14349653642693195105223607493513862832414933691226769073628840969955482975886 123
UVM_INFO @ 10157111109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 87229569253999924828815316525845540775894023659518986352387363725180840907665 121
UVM_INFO @ 10043352134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 41239087528279243678522318970439424104598555099881866126478153743135866179433 99
UVM_INFO @ 10023279065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 38284569249392663440671660249896449586604506678651086007392510141284423179268 88
UVM_INFO @ 10009874577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 41633713821084160298021584430252354981011252740998191935053794437523266362346 126
UVM_INFO @ 10042740413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 22380753259489822272026626224899740451617116611564989176572566878956272344026 186
UVM_INFO @ 10388377425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 80062439467822464632840597556301257052826301851542830769263106327745371681349 96
UVM_INFO @ 10029872926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 88557530658901649350158431055838124534728702503564177758517136137987209397205 92
UVM_INFO @ 10019628722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 15828738148359978048854190552105692190249741830945223348644744286572949952501 155
UVM_INFO @ 10061764122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 12 test runs
clkmgr_shadow_reg_errors 87454956217817241624346464887346439207499045336429413828293801107039226871162 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 99847559232204478510630887135736542432110682662649645650475053748230662652424 82
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 95511601507316678179847500367770850151408676222762624966091337598450747204775 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 1996785304499751308349970559414725649283183206799226669564538271606055288716 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 114925581122023506601271668408783662522567669140154860711063529759922842329622 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 58236301488402271328816869395864001954019462941463191860100399581377307442360 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 112177248464369097132309012738519406111097962070719047936126513707556480052455 82
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 38516278075912770276519489569155791172180589032733155701746392129113855576503 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 75751530247449949282153281537984680411498752012644212389882846480009437633070 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 45466036338406719876050882775640882139874992959166622502114830274988751089618 82
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 61242240520509049525319340237909386403354851529813001492427628738736978203710 81
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 100834597289100851181527272286394335549582990187374226348263783985871327027001 82
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 3 test runs
clkmgr_sec_cm 23937777413180123474405223174011388925577134725662929516943810895831594584580 84
UVM_INFO @ 1476741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 88806327478708503409418526502233055491021225760935529338101710911215188149215 84
UVM_INFO @ 2797261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 103152799224450499463725790551936251680250978263835802100979748602378471911268 122
UVM_INFO @ 102070684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.extclk_status (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 97736312931331531974791323883137676474053742998397803798663267584221671486718 81
UVM_INFO @ 2015943252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_enables (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 94553321860305902050563478695907817276948684116126062247297369369573484416876 82
UVM_INFO @ 2090623364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch 1 test run
clkmgr_clk_handshake_intersig_mubi 85028559143295327917686720292449695534033995474841407240349049409752051208224 80
UVM_INFO @ 2830345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---