Simulation Results: csrng

 
29/08/2026 03:59:48 DVSim: v1.49.0 sha: 0098135 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.87 %
  • code
  • 96.24 %
  • assert
  • 97.16 %
  • func
  • 91.21 %
  • block
  • 98.59 %
  • line
  • 99.54 %
  • branch
  • 96.55 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.85%
V2S
99.84%
V3
10.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 8.000s 57.185us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 4.000s 203.278us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 3.000s 50.904us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 16.000s 569.825us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 48.362us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 5.000s 263.196us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 3.000s 50.904us 5 5 100.00
csrng_csr_aliasing 3.000s 48.362us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 25.000s 1464.986us 200 200 100.00
alerts 500 500 100.00
csrng_alert 82.000s 5346.240us 500 500 100.00
err 500 500 100.00
csrng_err 13.000s 21.985us 500 500 100.00
cmds 25 25 100.00
csrng_cmds 621.000s 43888.244us 25 25 100.00
life cycle 25 25 100.00
csrng_cmds 621.000s 43888.244us 25 25 100.00
stress_all 23 25 92.00
csrng_stress_all 1475.000s 69625.711us 23 25 92.00
intr_test 10 10 100.00
csrng_intr_test 3.000s 30.215us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 3.000s 108.835us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 18.000s 691.257us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 18.000s 691.257us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 4.000s 203.278us 1 1 100.00
csrng_csr_rw 3.000s 50.904us 5 5 100.00
csrng_csr_aliasing 3.000s 48.362us 1 1 100.00
csrng_same_csr_outstanding 7.000s 241.943us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 4.000s 203.278us 1 1 100.00
csrng_csr_rw 3.000s 50.904us 5 5 100.00
csrng_csr_aliasing 3.000s 48.362us 1 1 100.00
csrng_same_csr_outstanding 7.000s 241.943us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
csrng_sec_cm 28.000s 612.859us 5 5 100.00
csrng_tl_intg_err 18.000s 989.016us 25 25 100.00
sec_cm_config_regwen 30 30 100.00
csrng_regwen 3.000s 77.779us 25 25 100.00
csrng_csr_rw 3.000s 50.904us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 82.000s 5346.240us 500 500 100.00
sec_cm_intersig_mubi 23 25 92.00
csrng_stress_all 1475.000s 69625.711us 23 25 92.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 25.000s 1464.986us 200 200 100.00
csrng_err 13.000s 21.985us 500 500 100.00
csrng_sec_cm 28.000s 612.859us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 25.000s 1464.986us 200 200 100.00
csrng_err 13.000s 21.985us 500 500 100.00
csrng_sec_cm 28.000s 612.859us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 25.000s 1464.986us 200 200 100.00
csrng_err 13.000s 21.985us 500 500 100.00
csrng_sec_cm 28.000s 612.859us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 25.000s 1464.986us 200 200 100.00
csrng_err 13.000s 21.985us 500 500 100.00
csrng_sec_cm 28.000s 612.859us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 25.000s 1464.986us 200 200 100.00
csrng_err 13.000s 21.985us 500 500 100.00
csrng_sec_cm 28.000s 612.859us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 82.000s 5346.240us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 25.000s 1464.986us 200 200 100.00
csrng_err 13.000s 21.985us 500 500 100.00
sec_cm_constants_lc_gated 23 25 92.00
csrng_stress_all 1475.000s 69625.711us 23 25 92.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 82.000s 5346.240us 500 500 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
csrng_tl_intg_err 18.000s 989.016us 25 25 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 25.000s 1464.986us 200 200 100.00
csrng_err 13.000s 21.985us 500 500 100.00
csrng_sec_cm 28.000s 612.859us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 25.000s 1464.986us 200 200 100.00
csrng_err 13.000s 21.985us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 25.000s 1464.986us 200 200 100.00
csrng_err 13.000s 21.985us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 25.000s 1464.986us 200 200 100.00
csrng_err 13.000s 21.985us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 25.000s 1464.986us 200 200 100.00
csrng_err 13.000s 21.985us 500 500 100.00
csrng_sec_cm 28.000s 612.859us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 25.000s 1464.986us 200 200 100.00
csrng_err 13.000s 21.985us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
csrng_stress_all_with_rand_reset 232.000s 6822.512us 1 10 10.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1230) [csrng_common_vseq] Check failed (vseq_done) 7 test runs
csrng_stress_all_with_rand_reset 64686549260830927084090468079992183409006038106248446817873455473381183108575 143
UVM_INFO @ 1107175428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 64461446829004710880669521271291100525181089109006148318922417815265825764351 158
UVM_INFO @ 851406647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 12418760838607703322281949193262839769385278407476322446262669329556626050281 118
UVM_INFO @ 3209778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 29559822048206192286630313304072050199040215636246987008678916122879155178106 106
UVM_INFO @ 82856101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 67451487419219386292726249383672869588336466275177771730869218294769849903259 219
UVM_INFO @ 2529830947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 13946643109866988993294253194872687070352584853614048207546160885347142818297 158
UVM_INFO @ 11802863757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 72904132645440339020542012172785015997610518663350833946665289800847682232803 112
UVM_INFO @ 3130931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:173) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 2 test runs
csrng_stress_all 1208368237424909475239440329069465556661083979124042399277909324154135590021 122
UVM_INFO @ 4450047331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 20057208674934794915404514364973636319124021007624614739757102376089302706204 106
UVM_INFO @ 77944181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_env_cfg.sv:359) [cfg] Check failed hw_key == * (* [*] vs * [*]) 1 test run
csrng_stress_all_with_rand_reset 54077962156172899196156048955056385529834510318984710339778083622016885406799 223
UVM_INFO @ 3406101356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_env_cfg.sv:358) [cfg] Check failed hw_v == * (* [*] vs * [*]) 1 test run
csrng_stress_all_with_rand_reset 71781303928173954165137048758094189369766969011453754160440042703434594454256 197
UVM_INFO @ 1046970455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---